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@@ -162,7 +162,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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}
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}
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-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
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/* MX1 and MX3 has one interrupt *per* gpio port */
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static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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@@ -174,9 +173,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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mxc_gpio_irq_handler(port, irq_stat);
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}
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-#endif
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-#ifdef CONFIG_ARCH_MX2
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/* MX2 has one interrupt *for all* gpio ports */
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static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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@@ -195,7 +192,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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mxc_gpio_irq_handler(&port[i], irq_stat);
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}
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}
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-#endif
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static struct irq_chip gpio_irq_chip = {
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.ack = gpio_ack_irq,
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@@ -284,17 +280,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
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/* its a serious configuration bug when it fails */
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BUG_ON( gpiochip_add(&port[i].chip) < 0 );
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-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
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- /* setup one handler for each entry */
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- set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
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- set_irq_data(port[i].irq, &port[i]);
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-#endif
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+ if (cpu_is_mx1() || cpu_is_mx3()) {
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+ /* setup one handler for each entry */
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+ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
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+ set_irq_data(port[i].irq, &port[i]);
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+ }
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+ }
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+
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+ if (cpu_is_mx2()) {
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+ /* setup one handler for all GPIO interrupts */
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+ set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
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+ set_irq_data(port[0].irq, port);
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}
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-#ifdef CONFIG_ARCH_MX2
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- /* setup one handler for all GPIO interrupts */
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- set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
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- set_irq_data(port[0].irq, port);
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-#endif
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return 0;
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}
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