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@@ -68,6 +68,9 @@ struct mlx4_mpt_entry {
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#define MLX4_MTT_FLAG_PRESENT 1
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+#define MLX4_MPT_STATUS_SW 0xF0
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+#define MLX4_MPT_STATUS_HW 0x00
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+
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static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
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{
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int o;
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@@ -469,3 +472,165 @@ void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
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mlx4_buddy_cleanup(&mr_table->mtt_buddy);
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mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
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}
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+
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+static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
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+ int npages, u64 iova)
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+{
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+ int i, page_mask;
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+
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+ if (npages > fmr->max_pages)
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+ return -EINVAL;
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+
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+ page_mask = (1 << fmr->page_shift) - 1;
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+
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+ /* We are getting page lists, so va must be page aligned. */
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+ if (iova & page_mask)
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+ return -EINVAL;
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+
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+ /* Trust the user not to pass misaligned data in page_list */
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+ if (0)
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+ for (i = 0; i < npages; ++i) {
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+ if (page_list[i] & ~page_mask)
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+ return -EINVAL;
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+ }
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+
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+ if (fmr->maps >= fmr->max_maps)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
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+ int npages, u64 iova, u32 *lkey, u32 *rkey)
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+{
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+ u32 key;
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+ int i, err;
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+
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+ err = mlx4_check_fmr(fmr, page_list, npages, iova);
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+ if (err)
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+ return err;
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+
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+ ++fmr->maps;
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+
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+ key = key_to_hw_index(fmr->mr.key);
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+ key += dev->caps.num_mpts;
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+ *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
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+
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+ *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
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+
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+ /* Make sure MPT status is visible before writing MTT entries */
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+ wmb();
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+
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+ for (i = 0; i < npages; ++i)
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+ fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
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+
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+ dma_sync_single(&dev->pdev->dev, fmr->dma_handle,
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+ npages * sizeof(u64), DMA_TO_DEVICE);
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+
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+ fmr->mpt->key = cpu_to_be32(key);
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+ fmr->mpt->lkey = cpu_to_be32(key);
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+ fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
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+ fmr->mpt->start = cpu_to_be64(iova);
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+
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+ /* Make MTT entries are visible before setting MPT status */
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+ wmb();
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+
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+ *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
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+
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+ /* Make sure MPT status is visible before consumer can use FMR */
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+ wmb();
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
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+
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+int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
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+ int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
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+{
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+ struct mlx4_priv *priv = mlx4_priv(dev);
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+ u64 mtt_seg;
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+ int err = -ENOMEM;
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+
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+ if (page_shift < 12 || page_shift >= 32)
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+ return -EINVAL;
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+
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+ /* All MTTs must fit in the same page */
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+ if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
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+ return -EINVAL;
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+
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+ fmr->page_shift = page_shift;
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+ fmr->max_pages = max_pages;
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+ fmr->max_maps = max_maps;
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+ fmr->maps = 0;
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+
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+ err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
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+ page_shift, &fmr->mr);
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+ if (err)
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+ return err;
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+
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+ mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
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+
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+ fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
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+ fmr->mr.mtt.first_seg,
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+ &fmr->dma_handle);
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+ if (!fmr->mtts) {
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+ err = -ENOMEM;
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+ goto err_free;
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+ }
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+
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+ fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
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+ key_to_hw_index(fmr->mr.key), NULL);
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+ if (!fmr->mpt) {
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+ err = -ENOMEM;
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+ goto err_free;
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+ }
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+
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+ return 0;
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+
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+err_free:
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+ mlx4_mr_free(dev, &fmr->mr);
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+ return err;
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+}
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+EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
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+
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+int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
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+{
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+ return mlx4_mr_enable(dev, &fmr->mr);
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+}
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+EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
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+
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+void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
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+ u32 *lkey, u32 *rkey)
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+{
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+ u32 key;
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+
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+ if (!fmr->maps)
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+ return;
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+
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+ key = key_to_hw_index(fmr->mr.key);
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+ key &= dev->caps.num_mpts - 1;
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+ *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
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+
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+ fmr->maps = 0;
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+
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+ *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
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+}
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+EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
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+
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+int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
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+{
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+ if (fmr->maps)
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+ return -EBUSY;
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+
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+ fmr->mr.enabled = 0;
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+ mlx4_mr_free(dev, &fmr->mr);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(mlx4_fmr_free);
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+
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+int mlx4_SYNC_TPT(struct mlx4_dev *dev)
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+{
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+ return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000);
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+}
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+EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);
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