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@@ -479,8 +479,24 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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case SQ_VSTMP_RING_ITEMSIZE:
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case VGT_TF_RING_SIZE:
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/* get value to populate the IB don't remove */
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- tmp =radeon_get_ib_value(p, idx);
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- ib[idx] = 0;
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+ /*tmp =radeon_get_ib_value(p, idx);
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+ ib[idx] = 0;*/
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+ break;
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+ case SQ_ESGS_RING_BASE:
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+ case SQ_GSVS_RING_BASE:
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+ case SQ_ESTMP_RING_BASE:
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+ case SQ_GSTMP_RING_BASE:
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+ case SQ_HSTMP_RING_BASE:
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+ case SQ_LSTMP_RING_BASE:
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+ case SQ_PSTMP_RING_BASE:
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+ case SQ_VSTMP_RING_BASE:
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+ r = evergreen_cs_packet_next_reloc(p, &reloc);
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+ if (r) {
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+ dev_warn(p->dev, "bad SET_CONTEXT_REG "
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+ "0x%04X\n", reg);
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+ return -EINVAL;
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+ }
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+ ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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break;
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case DB_DEPTH_CONTROL:
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track->db_depth_control = radeon_get_ib_value(p, idx);
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