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@@ -1148,25 +1148,25 @@ struct tx_status {
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#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
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/* CW RSSI for LCNPHY */
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-#define M_LCN_RSSI_0 0x1332
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-#define M_LCN_RSSI_1 0x1338
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-#define M_LCN_RSSI_2 0x133e
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-#define M_LCN_RSSI_3 0x1344
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+#define M_LCN_RSSI_0 0x1332
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+#define M_LCN_RSSI_1 0x1338
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+#define M_LCN_RSSI_2 0x133e
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+#define M_LCN_RSSI_3 0x1344
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/* SNR for LCNPHY */
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-#define M_LCN_SNR_A_0 0x1334
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-#define M_LCN_SNR_B_0 0x1336
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+#define M_LCN_SNR_A_0 0x1334
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+#define M_LCN_SNR_B_0 0x1336
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-#define M_LCN_SNR_A_1 0x133a
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-#define M_LCN_SNR_B_1 0x133c
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+#define M_LCN_SNR_A_1 0x133a
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+#define M_LCN_SNR_B_1 0x133c
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-#define M_LCN_SNR_A_2 0x1340
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-#define M_LCN_SNR_B_2 0x1342
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+#define M_LCN_SNR_A_2 0x1340
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+#define M_LCN_SNR_B_2 0x1342
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-#define M_LCN_SNR_A_3 0x1346
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-#define M_LCN_SNR_B_3 0x1348
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+#define M_LCN_SNR_A_3 0x1346
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+#define M_LCN_SNR_B_3 0x1348
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-#define M_LCN_LAST_RESET (81*2)
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+#define M_LCN_LAST_RESET (81*2)
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#define M_LCN_LAST_LOC (63*2)
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#define M_LCNPHY_RESET_STATUS (4902)
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#define M_LCNPHY_DSC_TIME (0x98d*2)
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@@ -1279,7 +1279,7 @@ struct shm_acparams {
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/* Flags in M_HOST_FLAGS4 */
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#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
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-#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
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+#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
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/* Flags in M_HOST_FLAGS5 */
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#define MHF5_4313_GPIOCTRL 0x0001
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@@ -1673,7 +1673,7 @@ struct macstat {
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#define BPHY_PEAK_ENERGY_HI 0x34
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#define BPHY_SYNC_CTL 0x35
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#define BPHY_TX_PWR_CTRL 0x36
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-#define BPHY_TX_EST_PWR 0x37
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+#define BPHY_TX_EST_PWR 0x37
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#define BPHY_STEP 0x38
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#define BPHY_WARMUP 0x39
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#define BPHY_LMS_CFF_READ 0x3a
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