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@@ -294,7 +294,6 @@ bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
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REG_WR(bp, BNX2_CTX_CTX_CTRL,
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offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
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for (i = 0; i < 5; i++) {
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- u32 val;
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val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
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if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
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break;
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@@ -7458,7 +7457,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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reg &= BNX2_CONDITION_MFW_RUN_MASK;
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if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
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reg != BNX2_CONDITION_MFW_RUN_NONE) {
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- int i;
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u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
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bp->fw_version[j++] = ' ';
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