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@@ -85,6 +85,9 @@ void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
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{
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{
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u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
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u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
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ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
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wait_done, false);
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wait_done, false);
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udelay(5);
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udelay(5);
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@@ -94,6 +97,9 @@ void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
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{
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{
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u32 payload = 0x00000000;
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u32 payload = 0x00000000;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
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ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
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wait_done, false);
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wait_done, false);
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}
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}
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@@ -107,6 +113,9 @@ static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
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void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
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void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
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{
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{
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
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ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
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NULL, 0, wait_done, false);
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NULL, 0, wait_done, false);
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}
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}
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@@ -220,6 +229,9 @@ void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 payload[4] = {0, 0, 0, 0};
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u32 payload[4] = {0, 0, 0, 0};
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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ath_dbg(common, MCI, "MCI Send Coex %s BT GPM\n",
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ath_dbg(common, MCI, "MCI Send Coex %s BT GPM\n",
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(halt) ? "halt" : "unhalt");
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(halt) ? "halt" : "unhalt");
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@@ -374,12 +386,17 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
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void ar9003_mci_disable_interrupt(struct ath_hw *ah)
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void ar9003_mci_disable_interrupt(struct ath_hw *ah)
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{
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{
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
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REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
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REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
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REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
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}
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}
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void ar9003_mci_enable_interrupt(struct ath_hw *ah)
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void ar9003_mci_enable_interrupt(struct ath_hw *ah)
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{
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{
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
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REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
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REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
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REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
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@@ -390,6 +407,9 @@ bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
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{
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{
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u32 intr;
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u32 intr;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return false;
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+
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intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
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intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
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return ((intr & ints) == ints);
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return ((intr & ints) == ints);
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}
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}
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@@ -398,6 +418,10 @@ void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
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u32 *rx_msg_intr)
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u32 *rx_msg_intr)
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{
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{
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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+
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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*raw_intr = mci->raw_intr;
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*raw_intr = mci->raw_intr;
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*rx_msg_intr = mci->rx_msg_intr;
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*rx_msg_intr = mci->rx_msg_intr;
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@@ -411,6 +435,9 @@ void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
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{
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{
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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if (!mci->update_2g5g &&
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if (!mci->update_2g5g &&
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(mci->is_2g != is_2g))
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(mci->is_2g != is_2g))
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mci->update_2g5g = true;
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mci->update_2g5g = true;
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@@ -524,6 +551,9 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 regval, thresh;
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u32 regval, thresh;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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ath_dbg(common, MCI, "MCI full_sleep = %d, is_2g = %d\n",
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ath_dbg(common, MCI, "MCI full_sleep = %d, is_2g = %d\n",
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is_full_sleep, is_2g);
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is_full_sleep, is_2g);
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@@ -650,6 +680,9 @@ void ar9003_mci_mute_bt(struct ath_hw *ah)
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{
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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/* disable all MCI messages */
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/* disable all MCI messages */
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REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
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REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
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REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
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REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
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@@ -682,6 +715,9 @@ void ar9003_mci_sync_bt_state(struct ath_hw *ah)
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 cur_bt_state;
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u32 cur_bt_state;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
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cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
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if (mci->bt_state != cur_bt_state) {
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if (mci->bt_state != cur_bt_state) {
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@@ -844,6 +880,9 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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if (mci->update_2g5g) {
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if (mci->update_2g5g) {
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if (mci->is_2g) {
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if (mci->is_2g) {
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@@ -895,6 +934,9 @@ bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
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u32 saved_mci_int_en;
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u32 saved_mci_int_en;
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int i;
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int i;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return false;
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+
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saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
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saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
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regval = REG_READ(ah, AR_BTCOEX_CTRL);
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regval = REG_READ(ah, AR_BTCOEX_CTRL);
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@@ -961,6 +1003,9 @@ void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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void *sched_buf = (void *)((char *) gpm_buf + (sched_addr - gpm_addr));
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void *sched_buf = (void *)((char *) gpm_buf + (sched_addr - gpm_addr));
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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mci->gpm_addr = gpm_addr;
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mci->gpm_addr = gpm_addr;
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mci->gpm_buf = gpm_buf;
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mci->gpm_buf = gpm_buf;
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mci->gpm_len = len;
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mci->gpm_len = len;
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@@ -975,6 +1020,9 @@ void ar9003_mci_cleanup(struct ath_hw *ah)
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{
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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+ if (!ATH9K_HW_CAP_MCI)
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+ return;
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+
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/* Turn off MCI and Jupiter mode. */
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/* Turn off MCI and Jupiter mode. */
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REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
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REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
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ath_dbg(common, MCI, "MCI ar9003_mci_cleanup\n");
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ath_dbg(common, MCI, "MCI ar9003_mci_cleanup\n");
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@@ -1039,6 +1087,9 @@ u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
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u8 recv_type = 0, recv_opcode = 0;
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u8 recv_type = 0, recv_opcode = 0;
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bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
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bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
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+ if (!ATH9K_HW_CAP_MCI)
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+ return 0;
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+
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more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
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more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
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while (time_out > 0) {
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while (time_out > 0) {
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@@ -1168,6 +1219,9 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
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u32 value = 0, more_gpm = 0, gpm_ptr;
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u32 value = 0, more_gpm = 0, gpm_ptr;
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u8 query_type;
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u8 query_type;
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+ if (!ATH9K_HW_CAP_MCI)
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+ return 0;
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+
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switch (state_type) {
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switch (state_type) {
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case MCI_STATE_ENABLE:
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case MCI_STATE_ENABLE:
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if (mci->ready) {
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if (mci->ready) {
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