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@@ -59,6 +59,9 @@ struct omap_mcpdm {
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/* McPDM FIFO thresholds */
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u32 dn_threshold;
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u32 up_threshold;
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+
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+ /* McPDM dn offsets for rx1, and 2 channels */
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+ u32 dn_rx_offset;
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};
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/*
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@@ -183,6 +186,15 @@ static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
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MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
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MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
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+ /* Enable DN RX1/2 offset cancellation feature, if configured */
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+ if (mcpdm->dn_rx_offset) {
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+ u32 dn_offset = mcpdm->dn_rx_offset;
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+
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+ omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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+ dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
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+ omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
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+ }
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+
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
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omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
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@@ -209,6 +221,10 @@ static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
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/* Disable DMA request generation for uplink */
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omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
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+
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+ /* Disable RX1/2 offset cancellation */
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+ if (mcpdm->dn_rx_offset)
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+ omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
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}
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static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
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@@ -418,6 +434,15 @@ static struct snd_soc_dai_driver omap_mcpdm_dai = {
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.ops = &omap_mcpdm_dai_ops,
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};
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+void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
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+ u8 rx1, u8 rx2)
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+{
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+ struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
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+
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+ mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
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+}
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+EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
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+
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static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
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{
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struct omap_mcpdm *mcpdm;
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