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@@ -339,10 +339,6 @@ ENTRY(pxa_cpu_resume)
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
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-#ifdef CONFIG_XSCALE_CACHE_ERRATA
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- bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
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-#endif
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-
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mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
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mcr p15, 0, r4, c15, c1, 0 @ CP access reg
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mcr p15, 0, r5, c13, c0, 0 @ PID
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@@ -368,9 +364,6 @@ sleep_save_sp:
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.text
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resume_after_mmu:
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-#ifdef CONFIG_XSCALE_CACHE_ERRATA
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- bl cpu_xscale_proc_init
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-#endif
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ldmfd sp!, {r2, r3}
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#ifndef CONFIG_IWMMXT
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mar acc0, r2, r3
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