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@@ -1,59 +1,26 @@
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/*
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- * <mach/asp.h> - DaVinci Audio Serial Port support
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+ * TI DaVinci Audio Serial Port support
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+ *
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+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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*/
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-#ifndef __ASM_ARCH_DAVINCI_ASP_H
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-#define __ASM_ARCH_DAVINCI_ASP_H
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-#include <mach/irqs.h>
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-#include <mach/edma.h>
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-
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-/* Bases of dm644x and dm355 register banks */
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-#define DAVINCI_ASP0_BASE 0x01E02000
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-#define DAVINCI_ASP1_BASE 0x01E04000
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-
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-/* Bases of dm365 register banks */
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-#define DAVINCI_DM365_ASP0_BASE 0x01D02000
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-
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-/* Bases of dm646x register banks */
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-#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
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-#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
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-
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-/* Bases of da850/da830 McASP0 register banks */
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-#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
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-
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-/* Bases of da830 McASP1 register banks */
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-#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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-
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-/* EDMA channels of dm644x and dm355 */
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-#define DAVINCI_DMA_ASP0_TX 2
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-#define DAVINCI_DMA_ASP0_RX 3
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-#define DAVINCI_DMA_ASP1_TX 8
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-#define DAVINCI_DMA_ASP1_RX 9
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-
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-/* EDMA channels of dm646x */
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-#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
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-#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
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-#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
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-
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-/* EDMA channels of da850/da830 McASP0 */
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-#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
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-#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
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-
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-/* EDMA channels of da830 McASP1 */
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-#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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-#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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-
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-/* Interrupts */
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-#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
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-#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
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-#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
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-#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
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+#ifndef __DAVINCI_ASP_H
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+#define __DAVINCI_ASP_H
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struct snd_platform_data {
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u32 tx_dma_offset;
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u32 rx_dma_offset;
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- enum dma_event_q asp_chan_q; /* event queue number for ASP channel */
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- enum dma_event_q ram_chan_q; /* event queue number for RAM channel */
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+ int asp_chan_q; /* event queue number for ASP channel */
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+ int ram_chan_q; /* event queue number for RAM channel */
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unsigned int codec_fmt;
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/*
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* Allowing this is more efficient and eliminates left and right swaps
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@@ -70,7 +37,7 @@ struct snd_platform_data {
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* and MCBSP_CLKS.
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* Depending on different hardware connections it is possible
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* to use this setting to change the behaviour of McBSP
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- * driver. The dm365_clk_input_pin enum is available for dm365
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+ * driver.
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*/
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int clk_input_pin;
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@@ -122,8 +89,8 @@ enum {
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MCASP_VERSION_2, /* DA8xx/OMAPL1x */
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};
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-enum dm365_clk_input_pin {
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- MCBSP_CLKR = 0, /* DM365 */
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+enum mcbsp_clk_input_pin {
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+ MCBSP_CLKR = 0, /* as in DM365 */
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MCBSP_CLKS,
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};
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@@ -134,4 +101,4 @@ enum dm365_clk_input_pin {
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#define DAVINCI_MCASP_IIS_MODE 0
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#define DAVINCI_MCASP_DIT_MODE 1
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-#endif /* __ASM_ARCH_DAVINCI_ASP_H */
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+#endif
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