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@@ -45,7 +45,7 @@ arrived in memory (this becomes more likely with devices behind PCI-PCI
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bridges). In order to ensure that all the data has arrived in memory,
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the interrupt handler must read a register on the device which raised
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the interrupt. PCI transaction ordering rules require that all the data
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-arrives in memory before the value can be returned from the register.
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+arrive in memory before the value may be returned from the register.
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Using MSIs avoids this problem as the interrupt-generating write cannot
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pass the data writes, so by the time the interrupt is raised, the driver
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knows that all the data has arrived in memory.
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