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@@ -2709,11 +2709,10 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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DRM_DEBUG_KMS("FDI train done.\n");
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}
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-static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
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+static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
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{
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- struct drm_device *dev = crtc->dev;
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+ struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 reg, temp;
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@@ -2754,6 +2753,35 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
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}
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}
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+static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
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+{
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+ struct drm_device *dev = intel_crtc->base.dev;
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ int pipe = intel_crtc->pipe;
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+ u32 reg, temp;
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+
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+ /* Switch from PCDclk to Rawclk */
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+ reg = FDI_RX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ I915_WRITE(reg, temp & ~FDI_PCDCLK);
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+
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+ /* Disable CPU FDI TX PLL */
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+ reg = FDI_TX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
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+
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+ POSTING_READ(reg);
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+ udelay(100);
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+
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+ reg = FDI_RX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
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+
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+ /* Wait for the clocks to turn off. */
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+ POSTING_READ(reg);
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+ udelay(100);
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+}
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+
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static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -3201,7 +3229,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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is_pch_port = intel_crtc_driving_pch(crtc);
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if (is_pch_port)
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- ironlake_fdi_pll_enable(crtc);
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+ ironlake_fdi_pll_enable(intel_crtc);
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else
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ironlake_fdi_disable(crtc);
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@@ -3304,26 +3332,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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/* disable PCH DPLL */
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intel_disable_pch_pll(intel_crtc);
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- /* Switch from PCDclk to Rawclk */
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- reg = FDI_RX_CTL(pipe);
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- temp = I915_READ(reg);
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- I915_WRITE(reg, temp & ~FDI_PCDCLK);
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-
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- /* Disable CPU FDI TX PLL */
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- reg = FDI_TX_CTL(pipe);
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- temp = I915_READ(reg);
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- I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
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-
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- POSTING_READ(reg);
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- udelay(100);
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-
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- reg = FDI_RX_CTL(pipe);
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- temp = I915_READ(reg);
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- I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
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-
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- /* Wait for the clocks to turn off. */
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- POSTING_READ(reg);
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- udelay(100);
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+ ironlake_fdi_pll_disable(intel_crtc);
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intel_crtc->active = false;
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intel_update_watermarks(dev);
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