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@@ -184,7 +184,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
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MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
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MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
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MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
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- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
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+ if (mcbsp->pdata->has_ccr) {
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MCBSP_WRITE(mcbsp, XCCR, config->xccr);
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MCBSP_WRITE(mcbsp, RCCR, config->rccr);
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}
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@@ -848,7 +848,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
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MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
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}
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- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
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+ if (mcbsp->pdata->has_ccr) {
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/* Release the transmitter and receiver */
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w = MCBSP_READ_CACHE(mcbsp, XCCR);
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w &= ~(tx ? XDISABLE : 0);
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@@ -878,7 +878,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
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/* Reset transmitter */
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tx &= 1;
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- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
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+ if (mcbsp->pdata->has_ccr) {
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w = MCBSP_READ_CACHE(mcbsp, XCCR);
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w |= (tx ? XDISABLE : 0);
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MCBSP_WRITE(mcbsp, XCCR, w);
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@@ -888,7 +888,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
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/* Reset receiver */
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rx &= 1;
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- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
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+ if (mcbsp->pdata->has_ccr) {
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w = MCBSP_READ_CACHE(mcbsp, RCCR);
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w |= (rx ? RDISABLE : 0);
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MCBSP_WRITE(mcbsp, RCCR, w);
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