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@@ -441,10 +441,11 @@ static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
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struct CommandControlBlock *ccb_tmp;
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struct CommandControlBlock *ccb_tmp;
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int i = 0, j = 0;
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int i = 0, j = 0;
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dma_addr_t cdb_phyaddr;
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dma_addr_t cdb_phyaddr;
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- unsigned long roundup_ccbsize = 0, offset;
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+ unsigned long roundup_ccbsize;
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unsigned long max_xfer_len;
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unsigned long max_xfer_len;
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unsigned long max_sg_entrys;
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unsigned long max_sg_entrys;
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uint32_t firm_config_version;
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uint32_t firm_config_version;
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+
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for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
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for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
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for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
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for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
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acb->devstate[i][j] = ARECA_RAID_GONE;
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acb->devstate[i][j] = ARECA_RAID_GONE;
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@@ -454,23 +455,20 @@ static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
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firm_config_version = acb->firm_cfg_version;
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firm_config_version = acb->firm_cfg_version;
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if((firm_config_version & 0xFF) >= 3){
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if((firm_config_version & 0xFF) >= 3){
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max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
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max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
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- max_sg_entrys = (max_xfer_len/4096);
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+ max_sg_entrys = (max_xfer_len/4096);
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}
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}
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acb->host->max_sectors = max_xfer_len/512;
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acb->host->max_sectors = max_xfer_len/512;
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acb->host->sg_tablesize = max_sg_entrys;
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acb->host->sg_tablesize = max_sg_entrys;
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roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
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roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
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- acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM + 32;
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+ acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
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dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
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dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
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if(!dma_coherent){
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if(!dma_coherent){
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- printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error \n", acb->host->host_no);
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+ printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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acb->dma_coherent = dma_coherent;
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acb->dma_coherent = dma_coherent;
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acb->dma_coherent_handle = dma_coherent_handle;
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acb->dma_coherent_handle = dma_coherent_handle;
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memset(dma_coherent, 0, acb->uncache_size);
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memset(dma_coherent, 0, acb->uncache_size);
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- offset = roundup((unsigned long)dma_coherent, 32) - (unsigned long)dma_coherent;
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- dma_coherent_handle = dma_coherent_handle + offset;
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- dma_coherent = (struct CommandControlBlock *)dma_coherent + offset;
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ccb_tmp = dma_coherent;
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ccb_tmp = dma_coherent;
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acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
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acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
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for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
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for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
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