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@@ -159,6 +159,36 @@ struct mlx5_reg_host_endianess {
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u8 rsvd[15];
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};
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+
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+#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
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+
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+enum {
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+ MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
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+ CAP_MASK(MLX5_CAP_OFF_DCT, 1),
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+};
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+
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+/* selectively copy writable fields clearing any reserved area
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+ */
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+static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from)
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+{
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+ u64 v64;
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+
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+ to->log_max_qp = from->log_max_qp & 0x1f;
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+ to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
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+ to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
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+ to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
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+ to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
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+ to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
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+ to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
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+ v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
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+ to->flags = cpu_to_be64(v64);
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+}
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+
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+enum {
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+ HCA_CAP_OPMOD_GET_MAX = 0,
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+ HCA_CAP_OPMOD_GET_CUR = 1,
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+};
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+
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static int handle_hca_cap(struct mlx5_core_dev *dev)
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{
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struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
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@@ -180,7 +210,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
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}
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query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
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- query_ctx.hdr.opmod = cpu_to_be16(0x1);
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+ query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
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err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
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query_out, sizeof(*query_out));
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if (err)
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@@ -192,8 +222,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
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goto query_ex;
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}
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- memcpy(&set_ctx->hca_cap, &query_out->hca_cap,
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- sizeof(set_ctx->hca_cap));
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+ copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);
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if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
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set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
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