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@@ -1,366 +0,0 @@
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-#include <linux/init.h>
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-#include <linux/kernel.h>
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-
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-#include <linux/string.h>
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-#include <linux/bitops.h>
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-#include <linux/smp.h>
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-#include <linux/thread_info.h>
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-#include <linux/module.h>
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-
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-#include <asm/processor.h>
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-#include <asm/pgtable.h>
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-#include <asm/msr.h>
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-#include <asm/uaccess.h>
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-#include <asm/ptrace.h>
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-#include <asm/ds.h>
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-#include <asm/bugs.h>
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-
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-#ifdef CONFIG_X86_64
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-#include <asm/topology.h>
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-#include <asm/numa_64.h>
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-#endif
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-
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-#include "cpu.h"
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-
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-#ifdef CONFIG_X86_LOCAL_APIC
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-#include <asm/mpspec.h>
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-#include <asm/apic.h>
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-#include <mach_apic.h>
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-#endif
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-
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-static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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-{
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- if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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- (c->x86 == 0x6 && c->x86_model >= 0x0e))
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- set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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-
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-#ifdef CONFIG_X86_64
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- set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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-#else
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- /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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- if (c->x86 == 15 && c->x86_cache_alignment == 64)
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- c->x86_cache_alignment = 128;
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-#endif
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-}
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-
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-#ifdef CONFIG_X86_32
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-/*
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- * Early probe support logic for ppro memory erratum #50
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- *
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- * This is called before we do cpu ident work
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- */
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-
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-int __cpuinit ppro_with_ram_bug(void)
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-{
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- /* Uses data from early_cpu_detect now */
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- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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- boot_cpu_data.x86 == 6 &&
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- boot_cpu_data.x86_model == 1 &&
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- boot_cpu_data.x86_mask < 8) {
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- printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
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- return 1;
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- }
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- return 0;
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-}
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-
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-
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-/*
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- * P4 Xeon errata 037 workaround.
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- * Hardware prefetcher may cause stale data to be loaded into the cache.
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- */
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-static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
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-{
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- unsigned long lo, hi;
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-
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- if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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- rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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- if ((lo & (1<<9)) == 0) {
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- printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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- printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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- lo |= (1<<9); /* Disable hw prefetching */
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- wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
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- }
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- }
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-}
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-
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-
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-
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-#ifdef CONFIG_X86_F00F_BUG
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-static void __cpuinit trap_init_f00f_bug(void)
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-{
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- __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
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-
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- /*
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- * Update the IDT descriptor and reload the IDT so that
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- * it uses the read-only mapped virtual address.
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- */
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- idt_descr.address = fix_to_virt(FIX_F00F_IDT);
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- load_idt(&idt_descr);
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-}
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-#endif
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-#endif
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-
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-static void __cpuinit srat_detect_node(void)
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-{
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-#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
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- unsigned node;
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- int cpu = smp_processor_id();
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- int apicid = hard_smp_processor_id();
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-
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- /* Don't do the funky fallback heuristics the AMD version employs
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- for now. */
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- node = apicid_to_node[apicid];
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- if (node == NUMA_NO_NODE || !node_online(node))
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- node = first_node(node_online_map);
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- numa_set_node(cpu, node);
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-
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- printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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-#endif
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-}
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-
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-/*
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- * find out the number of processor cores on the die
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- */
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-static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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-{
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- unsigned int eax, ebx, ecx, edx;
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-
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- if (c->cpuid_level < 4)
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- return 1;
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-
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- /* Intel has a non-standard dependency on %ecx for this CPUID level. */
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- cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
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- if (eax & 0x1f)
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- return ((eax >> 26) + 1);
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- else
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- return 1;
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-}
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-
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-static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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-{
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- unsigned int l2 = 0;
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- char *p = NULL;
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-
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- early_init_intel(c);
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-
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-#ifdef CONFIG_X86_F00F_BUG
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- /*
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- * All current models of Pentium and Pentium with MMX technology CPUs
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- * have the F0 0F bug, which lets nonprivileged users lock up the system.
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- * Note that the workaround only should be initialized once...
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- */
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- c->f00f_bug = 0;
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- if (!paravirt_enabled() && c->x86 == 5) {
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- static int f00f_workaround_enabled;
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-
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- c->f00f_bug = 1;
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- if (!f00f_workaround_enabled) {
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- trap_init_f00f_bug();
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- printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
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- f00f_workaround_enabled = 1;
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- }
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- }
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-#endif
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-
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- l2 = init_intel_cacheinfo(c);
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- if (c->cpuid_level > 9) {
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- unsigned eax = cpuid_eax(10);
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- /* Check for version and the number of counters */
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- if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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- set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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- }
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-
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-#ifdef CONFIG_X86_32
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- /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
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- if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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- clear_cpu_cap(c, X86_FEATURE_SEP);
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-
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- /*
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- * Names for the Pentium II/Celeron processors
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- * detectable only by also checking the cache size.
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- * Dixon is NOT a Celeron.
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- */
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- if (c->x86 == 6) {
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- switch (c->x86_model) {
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- case 5:
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- if (c->x86_mask == 0) {
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- if (l2 == 0)
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- p = "Celeron (Covington)";
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- else if (l2 == 256)
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- p = "Mobile Pentium II (Dixon)";
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- }
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- break;
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-
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- case 6:
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- if (l2 == 128)
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- p = "Celeron (Mendocino)";
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- else if (c->x86_mask == 0 || c->x86_mask == 5)
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- p = "Celeron-A";
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- break;
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-
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- case 8:
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- if (l2 == 128)
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- p = "Celeron (Coppermine)";
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- break;
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- }
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- }
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-
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- if (p)
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- strcpy(c->x86_model_id, p);
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-
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- Intel_errata_workarounds(c);
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-
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-#ifdef CONFIG_X86_INTEL_USERCOPY
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- /*
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- * Set up the preferred alignment for movsl bulk memory moves
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- */
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- switch (c->x86) {
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- case 4: /* 486: untested */
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- break;
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- case 5: /* Old Pentia: untested */
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- break;
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- case 6: /* PII/PIII only like movsl with 8-byte alignment */
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- movsl_mask.mask = 7;
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- break;
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- case 15: /* P4 is OK down to 8-byte alignment */
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- movsl_mask.mask = 7;
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- break;
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- }
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-#endif
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-
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-#endif
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-
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- if (cpu_has_xmm2)
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- set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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- if (cpu_has_ds) {
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- unsigned int l1;
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- rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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- if (!(l1 & (1<<11)))
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- set_cpu_cap(c, X86_FEATURE_BTS);
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- if (!(l1 & (1<<12)))
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- set_cpu_cap(c, X86_FEATURE_PEBS);
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- ds_init_intel(c);
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- }
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-
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-#ifdef CONFIG_X86_64
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- if (c->x86 == 15)
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- c->x86_cache_alignment = c->x86_clflush_size * 2;
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- if (c->x86 == 6)
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- set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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-#else
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- if (c->x86 == 15)
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- set_cpu_cap(c, X86_FEATURE_P4);
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- if (c->x86 == 6)
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- set_cpu_cap(c, X86_FEATURE_P3);
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-
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- if (cpu_has_bts)
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- ptrace_bts_init_intel(c);
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-
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- /*
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- * See if we have a good local APIC by checking for buggy Pentia,
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- * i.e. all B steppings and the C2 stepping of P54C when using their
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- * integrated APIC (see 11AP erratum in "Pentium Processor
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- * Specification Update").
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- */
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- if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
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- (c->x86_mask < 0x6 || c->x86_mask == 0xb))
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- set_cpu_cap(c, X86_FEATURE_11AP);
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-
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-#ifdef CONFIG_X86_NUMAQ
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- numaq_tsc_disable();
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-#endif
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-#endif
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-
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- detect_extended_topology(c);
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- if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
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- /*
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- * let's use the legacy cpuid vector 0x1 and 0x4 for topology
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- * detection.
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- */
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- c->x86_max_cores = intel_num_cpu_cores(c);
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-#ifdef CONFIG_X86_32
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- detect_ht(c);
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-#endif
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- }
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-
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- /* Work around errata */
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- srat_detect_node();
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-}
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-
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-#ifdef CONFIG_X86_32
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-static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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-{
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- /*
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- * Intel PIII Tualatin. This comes in two flavours.
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- * One has 256kb of cache, the other 512. We have no way
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- * to determine which, so we use a boottime override
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- * for the 512kb model, and assume 256 otherwise.
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- */
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- if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
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- size = 256;
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- return size;
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-}
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-#endif
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-
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-static struct cpu_dev intel_cpu_dev __cpuinitdata = {
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- .c_vendor = "Intel",
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- .c_ident = { "GenuineIntel" },
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-#ifdef CONFIG_X86_32
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- .c_models = {
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- { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
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- {
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- [0] = "486 DX-25/33",
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- [1] = "486 DX-50",
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- [2] = "486 SX",
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- [3] = "486 DX/2",
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- [4] = "486 SL",
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- [5] = "486 SX/2",
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- [7] = "486 DX/2-WB",
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- [8] = "486 DX/4",
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- [9] = "486 DX/4-WB"
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- }
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- },
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- { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
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- {
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- [0] = "Pentium 60/66 A-step",
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- [1] = "Pentium 60/66",
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- [2] = "Pentium 75 - 200",
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- [3] = "OverDrive PODP5V83",
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- [4] = "Pentium MMX",
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- [7] = "Mobile Pentium 75 - 200",
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- [8] = "Mobile Pentium MMX"
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- }
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- },
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- { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
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- {
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- [0] = "Pentium Pro A-step",
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- [1] = "Pentium Pro",
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- [3] = "Pentium II (Klamath)",
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- [4] = "Pentium II (Deschutes)",
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- [5] = "Pentium II (Deschutes)",
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- [6] = "Mobile Pentium II",
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- [7] = "Pentium III (Katmai)",
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- [8] = "Pentium III (Coppermine)",
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- [10] = "Pentium III (Cascades)",
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- [11] = "Pentium III (Tualatin)",
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- }
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- },
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- { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
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- {
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- [0] = "Pentium 4 (Unknown)",
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- [1] = "Pentium 4 (Willamette)",
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- [2] = "Pentium 4 (Northwood)",
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- [4] = "Pentium 4 (Foster)",
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- [5] = "Pentium 4 (Foster)",
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- }
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- },
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- },
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- .c_size_cache = intel_size_cache,
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-#endif
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- .c_early_init = early_init_intel,
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- .c_init = init_intel,
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- .c_x86_vendor = X86_VENDOR_INTEL,
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-};
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-
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-cpu_dev_register(intel_cpu_dev);
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-
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Yinghai Lu