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@@ -431,14 +431,16 @@ static void cx18_vbi_setup(struct cx18_stream *s)
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cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
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}
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-struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
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- struct cx18_buffer *buf)
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+static
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+struct cx18_queue *_cx18_stream_put_buf_fw(struct cx18_stream *s,
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+ struct cx18_buffer *buf)
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{
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struct cx18 *cx = s->cx;
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struct cx18_queue *q;
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/* Don't give it to the firmware, if we're not running a capture */
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if (s->handle == CX18_INVALID_TASK_HANDLE ||
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+ test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
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!test_bit(CX18_F_S_STREAMING, &s->s_flags))
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return cx18_enqueue(s, buf, &s->q_free);
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@@ -453,7 +455,8 @@ struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
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return q;
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}
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-void cx18_stream_load_fw_queue(struct cx18_stream *s)
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+static
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+void _cx18_stream_load_fw_queue(struct cx18_stream *s)
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{
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struct cx18_queue *q;
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struct cx18_buffer *buf;
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@@ -467,11 +470,93 @@ void cx18_stream_load_fw_queue(struct cx18_stream *s)
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buf = cx18_dequeue(s, &s->q_free);
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if (buf == NULL)
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break;
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- q = cx18_stream_put_buf_fw(s, buf);
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+ q = _cx18_stream_put_buf_fw(s, buf);
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} while (atomic_read(&s->q_busy.buffers) < CX18_MAX_FW_MDLS_PER_STREAM
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&& q == &s->q_busy);
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}
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+static inline
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+void free_out_work_order(struct cx18_out_work_order *order)
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+{
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+ atomic_set(&order->pending, 0);
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+}
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+
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+void cx18_out_work_handler(struct work_struct *work)
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+{
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+ struct cx18_out_work_order *order =
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+ container_of(work, struct cx18_out_work_order, work);
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+ struct cx18_stream *s = order->s;
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+ struct cx18_buffer *buf = order->buf;
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+
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+ free_out_work_order(order);
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+
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+ if (buf == NULL)
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+ _cx18_stream_load_fw_queue(s);
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+ else
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+ _cx18_stream_put_buf_fw(s, buf);
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+}
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+
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+static
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+struct cx18_out_work_order *alloc_out_work_order(struct cx18 *cx)
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+{
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+ int i;
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+ struct cx18_out_work_order *order = NULL;
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+
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+ for (i = 0; i < CX18_MAX_OUT_WORK_ORDERS; i++) {
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+ /*
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+ * We need "pending" to be atomic to inspect & set its contents
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+ * 1. "pending" is only set to 1 here, but needs multiple access
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+ * protection
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+ * 2. work handler threads only clear "pending" and only
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+ * on one, particular work order at a time, per handler thread.
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+ */
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+ if (atomic_add_unless(&cx->out_work_order[i].pending, 1, 1)) {
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+ order = &cx->out_work_order[i];
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+ break;
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+ }
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+ }
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+ return order;
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+}
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+
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+struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
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+ struct cx18_buffer *buf)
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+{
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+ struct cx18 *cx = s->cx;
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+ struct cx18_out_work_order *order;
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+
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+ order = alloc_out_work_order(cx);
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+ if (order == NULL) {
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+ CX18_DEBUG_WARN("No blank, outgoing-mailbox, deferred-work, "
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+ "order forms available; sending buffer %u back "
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+ "to the firmware immediately for stream %s\n",
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+ buf->id, s->name);
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+ return _cx18_stream_put_buf_fw(s, buf);
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+ }
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+ order->s = s;
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+ order->buf = buf;
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+ queue_work(cx->out_work_queue, &order->work);
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+ return NULL;
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+}
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+
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+void cx18_stream_load_fw_queue(struct cx18_stream *s)
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+{
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+ struct cx18 *cx = s->cx;
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+ struct cx18_out_work_order *order;
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+
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+ order = alloc_out_work_order(cx);
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+ if (order == NULL) {
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+ CX18_DEBUG_WARN("No blank, outgoing-mailbox, deferred-work, "
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+ "order forms available; filling the firmware "
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+ "buffer queue immediately for stream %s\n",
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+ s->name);
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+ _cx18_stream_load_fw_queue(s);
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+ return;
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+ }
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+ order->s = s;
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+ order->buf = NULL; /* Indicates to load the fw queue */
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+ queue_work(cx->out_work_queue, &order->work);
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+}
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+
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int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
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{
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u32 data[MAX_MB_ARGUMENTS];
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@@ -607,12 +692,13 @@ int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
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cx18_writel(cx, s->buf_size, &cx->scb->cpu_mdl[buf->id].length);
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}
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mutex_unlock(&s->qlock);
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- cx18_stream_load_fw_queue(s);
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+ _cx18_stream_load_fw_queue(s);
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/* begin_capture */
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if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
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CX18_DEBUG_WARN("Error starting capture!\n");
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/* Ensure we're really not capturing before releasing MDLs */
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+ set_bit(CX18_F_S_STOPPING, &s->s_flags);
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if (s->type == CX18_ENC_STREAM_TYPE_MPG)
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cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
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else
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@@ -622,6 +708,7 @@ int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
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cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
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cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
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s->handle = CX18_INVALID_TASK_HANDLE;
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+ clear_bit(CX18_F_S_STOPPING, &s->s_flags);
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if (atomic_read(&cx->tot_capturing) == 0) {
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set_bit(CX18_F_I_EOS, &cx->i_flags);
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cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
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@@ -666,6 +753,7 @@ int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
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if (atomic_read(&cx->tot_capturing) == 0)
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return 0;
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+ set_bit(CX18_F_S_STOPPING, &s->s_flags);
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if (s->type == CX18_ENC_STREAM_TYPE_MPG)
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cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
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else
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@@ -689,6 +777,7 @@ int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
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cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
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s->handle = CX18_INVALID_TASK_HANDLE;
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+ clear_bit(CX18_F_S_STOPPING, &s->s_flags);
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if (atomic_read(&cx->tot_capturing) > 0)
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return 0;
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