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@@ -782,7 +782,8 @@ static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
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return i == timeout_us / 10;
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}
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-int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, u32 len)
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+static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
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+ u32 len)
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{
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int err;
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u32 i, bufoff, msgoff, maxlen, apedata;
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@@ -7763,7 +7764,7 @@ static int tg3_alloc_consistent(struct tg3 *tp)
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sblk = tnapi->hw_status;
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if (tg3_flag(tp, ENABLE_RSS)) {
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- u16 *prodptr = 0;
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+ u16 *prodptr = NULL;
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/*
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* When RSS is enabled, the status block format changes
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@@ -8103,11 +8104,11 @@ static int tg3_chip_reset(struct tg3 *tp)
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u16 val16;
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if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
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- int i;
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+ int j;
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u32 cfg_val;
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/* Wait for link training to complete. */
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- for (i = 0; i < 5000; i++)
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+ for (j = 0; j < 5000; j++)
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udelay(100);
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pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
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@@ -10206,7 +10207,7 @@ static u32 tg3_irq_count(struct tg3 *tp)
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static bool tg3_enable_msix(struct tg3 *tp)
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{
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int i, rc;
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- struct msix_entry msix_ent[tp->irq_max];
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+ struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
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tp->txq_cnt = tp->txq_req;
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tp->rxq_cnt = tp->rxq_req;
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