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@@ -39,6 +39,7 @@ struct uda1380_priv {
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u16 reg_cache[UDA1380_CACHEREGNUM];
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unsigned int dac_clk;
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struct work_struct work;
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+ void *control_data;
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};
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/*
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@@ -129,7 +130,46 @@ static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
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return -EIO;
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}
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-#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
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+static void uda1380_sync_cache(struct snd_soc_codec *codec)
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+{
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+ int reg;
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+ u8 data[3];
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+ u16 *cache = codec->reg_cache;
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+
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+ /* Sync reg_cache with the hardware */
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+ for (reg = 0; reg < UDA1380_MVOL; reg++) {
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+ data[0] = reg;
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+ data[1] = (cache[reg] & 0xff00) >> 8;
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+ data[2] = cache[reg] & 0x00ff;
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+ if (codec->hw_write(codec->control_data, data, 3) != 3)
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+ dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
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+ __func__, reg);
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+ }
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+}
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+
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+static int uda1380_reset(struct snd_soc_codec *codec)
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+{
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+ struct uda1380_platform_data *pdata = codec->dev->platform_data;
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+
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+ if (gpio_is_valid(pdata->gpio_reset)) {
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+ gpio_set_value(pdata->gpio_reset, 1);
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+ mdelay(1);
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+ gpio_set_value(pdata->gpio_reset, 0);
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+ } else {
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+ u8 data[3];
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+
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+ data[0] = UDA1380_RESET;
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+ data[1] = 0;
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+ data[2] = 0;
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+
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+ if (codec->hw_write(codec->control_data, data, 3) != 3) {
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+ dev_err(codec->dev, "%s: failed\n", __func__);
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+ return -EIO;
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+ }
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+ }
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+
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+ return 0;
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+}
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static void uda1380_flush_work(struct work_struct *work)
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{
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@@ -560,18 +600,40 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
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+ int reg;
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+ struct uda1380_platform_data *pdata = codec->dev->platform_data;
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+
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+ if (codec->bias_level == level)
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+ return 0;
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switch (level) {
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case SND_SOC_BIAS_ON:
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case SND_SOC_BIAS_PREPARE:
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+ /* ADC, DAC on */
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uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
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break;
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case SND_SOC_BIAS_STANDBY:
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- uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
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- break;
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- case SND_SOC_BIAS_OFF:
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+ if (codec->bias_level == SND_SOC_BIAS_OFF) {
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+ if (gpio_is_valid(pdata->gpio_power)) {
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+ gpio_set_value(pdata->gpio_power, 1);
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+ uda1380_reset(codec);
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+ }
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+
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+ uda1380_sync_cache(codec);
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+ }
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uda1380_write(codec, UDA1380_PM, 0x0);
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break;
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+ case SND_SOC_BIAS_OFF:
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+ if (!gpio_is_valid(pdata->gpio_power))
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+ break;
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+
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+ gpio_set_value(pdata->gpio_power, 0);
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+
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+ /* Mark mixer regs cache dirty to sync them with
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+ * codec regs on power on.
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+ */
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+ for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
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+ set_bit(reg - 0x10, &uda1380_cache_dirty);
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}
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codec->bias_level = level;
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return 0;
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@@ -651,16 +713,6 @@ static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
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static int uda1380_resume(struct snd_soc_codec *codec)
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{
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- int i;
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- u8 data[2];
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- u16 *cache = codec->reg_cache;
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-
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- /* Sync reg_cache with the hardware */
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- for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
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- data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
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- data[1] = cache[i] & 0x00ff;
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- codec->hw_write(codec->control_data, data, 2);
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- }
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uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
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return 0;
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}
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@@ -671,29 +723,36 @@ static int uda1380_probe(struct snd_soc_codec *codec)
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struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
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int ret;
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+ uda1380->codec = codec;
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+
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codec->hw_write = (hw_write_t)i2c_master_send;
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+ codec->control_data = uda1380->control_data;
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- if (!pdata || !pdata->gpio_power || !pdata->gpio_reset)
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+ if (!pdata)
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return -EINVAL;
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- ret = gpio_request(pdata->gpio_power, "uda1380 power");
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- if (ret)
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- return ret;
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- ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
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- if (ret)
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- goto err_gpio;
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-
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- gpio_direction_output(pdata->gpio_power, 1);
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-
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- /* we may need to have the clock running here - pH5 */
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- gpio_direction_output(pdata->gpio_reset, 1);
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- udelay(5);
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- gpio_set_value(pdata->gpio_reset, 0);
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+ if (gpio_is_valid(pdata->gpio_reset)) {
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+ ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
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+ if (ret)
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+ goto err_out;
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+ ret = gpio_direction_output(pdata->gpio_reset, 0);
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+ if (ret)
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+ goto err_gpio_reset_conf;
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+ }
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- ret = uda1380_reset(codec);
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- if (ret < 0) {
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- dev_err(codec->dev, "Failed to issue reset\n");
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- goto err_reset;
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+ if (gpio_is_valid(pdata->gpio_power)) {
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+ ret = gpio_request(pdata->gpio_power, "uda1380 power");
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+ if (ret)
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+ goto err_gpio;
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+ ret = gpio_direction_output(pdata->gpio_power, 0);
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+ if (ret)
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+ goto err_gpio_power_conf;
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+ } else {
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+ ret = uda1380_reset(codec);
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+ if (ret) {
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+ dev_err(codec->dev, "Failed to issue reset\n");
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+ goto err_reset;
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+ }
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}
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INIT_WORK(&uda1380->work, uda1380_flush_work);
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@@ -703,10 +762,11 @@ static int uda1380_probe(struct snd_soc_codec *codec)
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/* set clock input */
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switch (pdata->dac_clk) {
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case UDA1380_DAC_CLK_SYSCLK:
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- uda1380_write(codec, UDA1380_CLK, 0);
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+ uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
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break;
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case UDA1380_DAC_CLK_WSPLL:
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- uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
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+ uda1380_write_reg_cache(codec, UDA1380_CLK,
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+ R00_DAC_CLK);
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break;
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}
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@@ -717,10 +777,15 @@ static int uda1380_probe(struct snd_soc_codec *codec)
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return 0;
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err_reset:
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- gpio_set_value(pdata->gpio_power, 0);
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- gpio_free(pdata->gpio_reset);
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+err_gpio_power_conf:
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+ if (gpio_is_valid(pdata->gpio_power))
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+ gpio_free(pdata->gpio_power);
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+
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+err_gpio_reset_conf:
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err_gpio:
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- gpio_free(pdata->gpio_power);
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+ if (gpio_is_valid(pdata->gpio_reset))
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+ gpio_free(pdata->gpio_reset);
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+err_out:
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return ret;
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}
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@@ -731,7 +796,6 @@ static int uda1380_remove(struct snd_soc_codec *codec)
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uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
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- gpio_set_value(pdata->gpio_power, 0);
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gpio_free(pdata->gpio_reset);
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gpio_free(pdata->gpio_power);
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@@ -743,8 +807,8 @@ static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
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.remove = uda1380_remove,
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.suspend = uda1380_suspend,
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.resume = uda1380_resume,
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- .read = uda1380_read_reg_cache,
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- .write = uda1380_write,
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+ .read = uda1380_read_reg_cache,
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+ .write = uda1380_write,
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.set_bias_level = uda1380_set_bias_level,
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.reg_cache_size = ARRAY_SIZE(uda1380_reg),
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.reg_word_size = sizeof(u16),
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@@ -764,6 +828,7 @@ static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
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return -ENOMEM;
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i2c_set_clientdata(i2c, uda1380);
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+ uda1380->control_data = i2c;
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ret = snd_soc_register_codec(&i2c->dev,
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&soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
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