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@@ -148,15 +148,13 @@ __asm__(
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#endif
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/*
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- * mtc0->mfc0 hazard
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- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
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- * It is a MIPS32R2 processor so ehb will clear the hazard.
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+ * Interrupt enable/disable hazards
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+ * Some processors have hazards when modifying
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+ * the status register to change the interrupt state
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*/
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#ifdef CONFIG_CPU_MIPSR2
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-/*
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- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
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- */
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+
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__asm__(
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" .macro\tirq_enable_hazard \n\t"
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" _ehb \n\t"
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@@ -164,19 +162,23 @@ __asm__(
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" \n\t"
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" .macro\tirq_disable_hazard \n\t"
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" _ehb \n\t"
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+ " .endm \n\t"
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+ " \n\t"
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+ " .macro\tback_to_back_c0_hazard \n\t"
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+ " _ehb \n\t"
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" .endm");
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#define irq_enable_hazard() \
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__asm__ __volatile__( \
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- "_ehb\t\t\t\t# irq_enable_hazard")
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+ "irq_enable_hazard")
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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- "_ehb\t\t\t\t# irq_disable_hazard")
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+ "irq_disable_hazard")
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__( \
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- "_ehb\t\t\t\t# back_to_back_c0_hazard")
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+ "back_to_back_c0_hazard")
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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@@ -218,7 +220,7 @@ __asm__(
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#define irq_enable_hazard() do { } while (0)
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#define irq_disable_hazard() \
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__asm__ __volatile__( \
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- "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
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+ "irq_disable_hazard")
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__( \
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Ralf Baechle