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@@ -149,12 +149,6 @@ unsigned long *sparc64_valid_addr_bitmap __read_mostly;
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unsigned long kern_base __read_mostly;
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unsigned long kern_size __read_mostly;
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-/* get_new_mmu_context() uses "cache + 1". */
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-DEFINE_SPINLOCK(ctx_alloc_lock);
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-unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
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-#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
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-unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
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-
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/* Initial ramdisk setup */
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extern unsigned long sparc_ramdisk_image64;
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extern unsigned int sparc_ramdisk_image;
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@@ -701,6 +695,13 @@ void __flush_dcache_range(unsigned long start, unsigned long end)
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}
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#endif /* DCACHE_ALIASING_POSSIBLE */
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+/* get_new_mmu_context() uses "cache + 1". */
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+DEFINE_SPINLOCK(ctx_alloc_lock);
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+unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
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+#define MAX_CTX_NR (1UL << CTX_NR_BITS)
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+#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
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+DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
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+
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/* Caller does TLB context flushing on local CPU if necessary.
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* The caller also ensures that CTX_VALID(mm->context) is false.
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*
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