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+/*
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+ * linux/arch/arm/plat-omap/i2c.c
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+ *
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+ * Helper module for board specific I2C bus registration
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+ *
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+ * Copyright (C) 2007 Nokia Corporation.
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+ *
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+ * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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+ * 02110-1301 USA
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/platform_device.h>
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+#include <linux/i2c.h>
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+#include <asm/mach-types.h>
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+#include <asm/arch/mux.h>
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+
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+#define OMAP_I2C_SIZE 0x3f
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+#define OMAP1_I2C_BASE 0xfffb3800
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+#define OMAP2_I2C_BASE1 0x48070000
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+#define OMAP2_I2C_BASE2 0x48072000
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+#define OMAP2_I2C_BASE3 0x48060000
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+
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+static const char name[] = "i2c_omap";
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+
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+#define I2C_RESOURCE_BUILDER(base, irq) \
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+ { \
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+ .start = (base), \
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+ .end = (base) + OMAP_I2C_SIZE, \
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+ .flags = IORESOURCE_MEM, \
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+ }, \
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+ { \
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+ .start = (irq), \
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+ .flags = IORESOURCE_IRQ, \
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+ },
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+
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+static struct resource i2c_resources[][2] = {
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+ { I2C_RESOURCE_BUILDER(0, 0) },
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+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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+ { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
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+#endif
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+#if defined(CONFIG_ARCH_OMAP34XX)
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+ { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
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+#endif
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+};
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+
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+#define I2C_DEV_BUILDER(bus_id, res, data) \
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+ { \
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+ .id = (bus_id), \
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+ .name = name, \
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+ .num_resources = ARRAY_SIZE(res), \
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+ .resource = (res), \
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+ .dev = { \
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+ .platform_data = (data), \
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+ }, \
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+ }
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+
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+static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
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+static struct platform_device omap_i2c_devices[] = {
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+ I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
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+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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+ I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
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+#endif
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+#if defined(CONFIG_ARCH_OMAP34XX)
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+ I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
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+#endif
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+};
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+
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+static void __init omap_i2c_mux_pins(int bus_id)
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+{
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+ /* TODO: Muxing for OMAP3 */
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+ switch (bus_id) {
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+ case 1:
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+ if (cpu_class_is_omap1()) {
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+ omap_cfg_reg(I2C_SCL);
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+ omap_cfg_reg(I2C_SDA);
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+ } else if (cpu_is_omap24xx()) {
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+ omap_cfg_reg(M19_24XX_I2C1_SCL);
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+ omap_cfg_reg(L15_24XX_I2C1_SDA);
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+ }
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+ break;
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+ case 2:
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+ if (cpu_is_omap24xx()) {
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+ omap_cfg_reg(J15_24XX_I2C2_SCL);
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+ omap_cfg_reg(H19_24XX_I2C2_SDA);
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+ }
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+ break;
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+ }
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+}
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+
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+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
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+ struct i2c_board_info const *info,
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+ unsigned len)
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+{
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+ int ports, err;
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+ struct platform_device *pdev;
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+ struct resource *res;
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+ resource_size_t base, irq;
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+
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+ if (cpu_class_is_omap1())
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+ ports = 1;
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+ else if (cpu_is_omap24xx())
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+ ports = 2;
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+ else if (cpu_is_omap34xx())
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+ ports = 3;
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+
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+ BUG_ON(bus_id < 1 || bus_id > ports);
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+
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+ if (info) {
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+ err = i2c_register_board_info(bus_id, info, len);
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+ if (err)
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+ return err;
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+ }
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+
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+ pdev = &omap_i2c_devices[bus_id - 1];
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+ *(u32 *)pdev->dev.platform_data = clkrate;
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+
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+ if (bus_id == 1) {
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+ res = pdev->resource;
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+ if (cpu_class_is_omap1()) {
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+ base = OMAP1_I2C_BASE;
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+ irq = INT_I2C;
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+ } else {
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+ base = OMAP2_I2C_BASE1;
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+ irq = INT_24XX_I2C1_IRQ;
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+ }
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+ res[0].start = base;
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+ res[0].end = base + OMAP_I2C_SIZE;
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+ res[1].start = irq;
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+ }
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+
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+ omap_i2c_mux_pins(bus_id);
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+ return platform_device_register(pdev);
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+}
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