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@@ -7,39 +7,12 @@
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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-#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <loongson.h>
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-/*
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- * the first level int-handler will jump here if it is a bonito irq
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- */
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-static void bonito_irqdispatch(void)
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-{
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- u32 int_status;
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- int i;
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-
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- /* workaround the IO dma problem: let cpu looping to allow DMA finish */
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- int_status = BONITO_INTISR;
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- if (int_status & (1 << 10)) {
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- while (int_status & (1 << 10)) {
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- udelay(1);
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- int_status = BONITO_INTISR;
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- }
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- }
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-
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- /* Get pending sources, masked by current enables */
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- int_status = BONITO_INTISR & BONITO_INTEN;
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-
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- if (int_status != 0) {
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- i = __ffs(int_status);
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- int_status &= ~(1 << i);
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- do_IRQ(BONITO_IRQ_BASE + i);
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- }
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-}
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static void i8259_irqdispatch(void)
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{
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@@ -52,10 +25,8 @@ static void i8259_irqdispatch(void)
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spurious_interrupt();
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}
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-asmlinkage void plat_irq_dispatch(void)
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+asmlinkage void mach_irq_dispatch(unsigned int pending)
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{
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- unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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-
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if (pending & CAUSEF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else if (pending & CAUSEF_IP6) /* perf counter loverflow */
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@@ -73,26 +44,15 @@ static struct irqaction cascade_irqaction = {
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.name = "cascade",
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};
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-void __init arch_init_irq(void)
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+void __init set_irq_trigger_mode(void)
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{
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- /*
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- * Clear all of the interrupts while we change the able around a bit.
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- * int-handler is not on bootstrap
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- */
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- clear_c0_status(ST0_IM | ST0_BEV);
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- local_irq_disable();
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-
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/* most bonito irq should be level triggered */
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BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
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- BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
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- BONITO_INTSTEER = 0;
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-
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- /*
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- * Mask out all interrupt by writing "1" to all bit position in
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- * the interrupt reset reg.
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- */
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- BONITO_INTENCLR = ~0;
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+ BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
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+}
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+void __init mach_init_irq(void)
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+{
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/* init all controller
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* 0-15 ------> i8259 interrupt
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* 16-23 ------> mips cpu interrupt
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