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@@ -822,8 +822,7 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
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}
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-static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
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- int ganged);
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+static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
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static void amd64_dump_dramcfg_low(u32 dclr, int chan)
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{
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@@ -875,8 +874,10 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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(pvt->dhar & DHAR_VALID) ? "yes" : "no");
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/* everything below this point is Fam10h and above */
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- if (boot_cpu_data.x86 == 0xf)
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+ if (boot_cpu_data.x86 == 0xf) {
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+ amd64_debug_display_dimm_sizes(0, pvt);
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return;
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+ }
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/* Only if NOT ganged does dclr1 have valid info */
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if (!dct_ganging_enabled(pvt))
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@@ -888,10 +889,10 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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*/
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ganged = dct_ganging_enabled(pvt);
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- f10_debug_display_dimm_sizes(0, pvt, ganged);
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+ amd64_debug_display_dimm_sizes(0, pvt);
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if (!ganged)
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- f10_debug_display_dimm_sizes(1, pvt, ganged);
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+ amd64_debug_display_dimm_sizes(1, pvt);
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}
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/* Read in both of DBAM registers */
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@@ -1726,23 +1727,31 @@ static int map_dbam_to_csrow_size(int index)
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}
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/*
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- * debug routine to display the memory sizes of a DIMM (ganged or not) and it
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+ * debug routine to display the memory sizes of all logical DIMMs and its
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* CSROWs as well
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*/
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-static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
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- int ganged)
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+static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
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{
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int dimm, size0, size1;
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u32 dbam;
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u32 *dcsb;
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- debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl,
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- ctrl ? pvt->dbam1 : pvt->dbam0,
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- ganged ? "GANGED - dbam1 not used" : "NON-GANGED");
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+ if (boot_cpu_data.x86 == 0xf) {
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+ /* K8 families < revF not supported yet */
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+ if (pvt->ext_model < OPTERON_CPU_REV_F)
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+ return;
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+ else
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+ WARN_ON(ctrl != 0);
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+ }
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+
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+ debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
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+ ctrl, ctrl ? pvt->dbam1 : pvt->dbam0);
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dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
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dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
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+ edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
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+
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/* Dump memory sizes for DIMM and its CSROWs */
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for (dimm = 0; dimm < 4; dimm++) {
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@@ -1754,15 +1763,8 @@ static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
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if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE)
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size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam));
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- debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB "
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- "CSROW-%d=%5dMB\n",
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- ctrl,
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- dimm,
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- size0 + size1,
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- dimm * 2,
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- size0,
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- dimm * 2 + 1,
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- size1);
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+ edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n",
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+ dimm * 2, size0, dimm * 2 + 1, size1);
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}
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}
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