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@@ -1480,7 +1480,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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"requested.\n",
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tp->dev->name, state);
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return -EINVAL;
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- };
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+ }
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power_control |= PCI_PM_CTRL_PME_ENABLE;
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@@ -1906,7 +1906,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
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*speed = SPEED_INVALID;
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*duplex = DUPLEX_INVALID;
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break;
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- };
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+ }
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}
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static void tg3_phy_copper_begin(struct tg3 *tp)
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@@ -2018,7 +2018,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
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case SPEED_1000:
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bmcr |= TG3_BMCR_SPEED1000;
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break;
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- };
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+ }
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if (tp->link_config.duplex == DUPLEX_FULL)
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bmcr |= BMCR_FULLDPLX;
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@@ -2716,7 +2716,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
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default:
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ret = ANEG_FAILED;
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break;
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- };
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+ }
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return ret;
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}
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@@ -3558,7 +3558,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
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default:
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return -EINVAL;
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- };
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+ }
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/* Do not overwrite any of the map or rp information
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* until we are sure we can commit to a new buffer.
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@@ -3618,7 +3618,7 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
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default:
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return;
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- };
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+ }
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dest_map->skb = src_map->skb;
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pci_unmap_addr_set(dest_map, mapping,
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@@ -4961,7 +4961,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
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default:
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break;
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- };
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+ }
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}
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val = tr32(ofs);
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@@ -5203,7 +5203,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
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default:
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break;
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- };
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+ }
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}
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if (kind == RESET_KIND_INIT ||
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@@ -5228,7 +5228,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
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default:
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break;
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- };
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+ }
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}
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if (kind == RESET_KIND_SHUTDOWN)
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@@ -5257,7 +5257,7 @@ static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
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default:
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break;
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- };
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+ }
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}
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}
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@@ -7282,7 +7282,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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default:
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break;
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- };
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+ }
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
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/* Write our heartbeat update interval to APE. */
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@@ -10879,7 +10879,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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LED_CTRL_MODE_PHY_2);
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break;
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- };
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+ }
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
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@@ -12178,7 +12178,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
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DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
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break;
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- };
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+ }
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} else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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switch (cacheline_size) {
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case 16:
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@@ -12195,7 +12195,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
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val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
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break;
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- };
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+ }
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} else {
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switch (cacheline_size) {
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case 16:
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@@ -12239,7 +12239,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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val |= (DMA_RWCTRL_READ_BNDRY_1024 |
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DMA_RWCTRL_WRITE_BNDRY_1024);
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break;
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- };
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+ }
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}
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out:
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@@ -12599,7 +12599,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
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case PHY_ID_BCM8002: return "8002/serdes";
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case 0: return "serdes";
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default: return "unknown";
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- };
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+ }
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}
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static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
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