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@@ -181,7 +181,11 @@
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
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/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
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-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
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+/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
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+ * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
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+ * after the behavior and the root cause are confirmed with hardware team.
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+ */
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+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
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/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
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#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
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/* ICPLB_STATUS MMR Register May Be Corrupted */
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