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@@ -173,8 +173,10 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
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udelay(15);
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udelay(15);
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if (ah->ah_version == AR5K_AR5210) {
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if (ah->ah_version == AR5K_AR5210) {
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- val &= AR5K_RESET_CTL_CHIP;
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- mask &= AR5K_RESET_CTL_CHIP;
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+ val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
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+ | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
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+ mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
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+ | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
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} else {
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} else {
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val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
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val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
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mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
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mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
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@@ -361,16 +363,20 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
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bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
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/* Reset chipset */
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/* Reset chipset */
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- ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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- AR5K_RESET_CTL_BASEBAND | bus_flags);
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+ if (ah->ah_version == AR5K_AR5210) {
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+ ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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+ AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
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+ AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
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+ mdelay(2);
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+ } else {
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+ ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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+ AR5K_RESET_CTL_BASEBAND | bus_flags);
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+ }
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if (ret) {
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
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ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
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return -EIO;
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return -EIO;
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}
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}
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- if (ah->ah_version == AR5K_AR5210)
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- udelay(2300);
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-
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/* ...wakeup again!*/
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/* ...wakeup again!*/
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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if (ret) {
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