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@@ -1449,6 +1449,16 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
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"0x%x data 0x%llx\n", msr, data);
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break;
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+ case MSR_K7_CLK_CTL:
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+ /*
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+ * Ignore all writes to this no longer documented MSR.
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+ * Writes are only relevant for old K7 processors,
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+ * all pre-dating SVM, but a recommended workaround from
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+ * AMD for these chips. It is possible to speicify the
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+ * affected processor models on the command line, hence
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+ * the need to ignore the workaround.
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+ */
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+ break;
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case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
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if (kvm_hv_msr_partition_wide(msr)) {
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int r;
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@@ -1674,6 +1684,18 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
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return get_msr_mce(vcpu, msr, pdata);
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+ case MSR_K7_CLK_CTL:
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+ /*
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+ * Provide expected ramp-up count for K7. All other
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+ * are set to zero, indicating minimum divisors for
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+ * every field.
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+ *
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+ * This prevents guest kernels on AMD host with CPU
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+ * type 6, model 8 and higher from exploding due to
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+ * the rdmsr failing.
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+ */
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+ data = 0x20000000;
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+ break;
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case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
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if (kvm_hv_msr_partition_wide(msr)) {
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int r;
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