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@@ -7,9 +7,65 @@
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#define IOP_TMR_PRIVILEGED 0x08
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#define IOP_TMR_RATIO_1_1 0x00
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+#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
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+#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
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+#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
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+#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
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+#define IOP13XX_CORE_FREQ_MASK (7 << 16)
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+#define IOP13XX_CORE_FREQ_600 (0 << 16)
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+#define IOP13XX_CORE_FREQ_667 (1 << 16)
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+#define IOP13XX_CORE_FREQ_800 (2 << 16)
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+#define IOP13XX_CORE_FREQ_933 (3 << 16)
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+#define IOP13XX_CORE_FREQ_1000 (4 << 16)
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+#define IOP13XX_CORE_FREQ_1200 (5 << 16)
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+
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void iop_init_time(unsigned long tickrate);
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unsigned long iop_gettimeoffset(void);
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+static inline unsigned long iop13xx_core_freq(void)
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+{
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+ unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
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+ freq &= IOP13XX_CORE_FREQ_MASK;
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+ switch (freq) {
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+ case IOP13XX_CORE_FREQ_600:
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+ return 600000000;
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+ case IOP13XX_CORE_FREQ_667:
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+ return 667000000;
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+ case IOP13XX_CORE_FREQ_800:
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+ return 800000000;
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+ case IOP13XX_CORE_FREQ_933:
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+ return 933000000;
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+ case IOP13XX_CORE_FREQ_1000:
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+ return 1000000000;
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+ case IOP13XX_CORE_FREQ_1200:
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+ return 1200000000;
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+ default:
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+ printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
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+ __FUNCTION__);
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+ }
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+
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+ return 800000000;
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+}
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+
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+static inline unsigned long iop13xx_xsi_bus_ratio(void)
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+{
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+ unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
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+ ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
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+ switch (ratio) {
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+ case IOP13XX_XSI_FREQ_RATIO_2:
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+ return 2;
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+ case IOP13XX_XSI_FREQ_RATIO_3:
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+ return 3;
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+ case IOP13XX_XSI_FREQ_RATIO_4:
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+ return 4;
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+ default:
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+ printk("%s: warning unknown ratio, defaulting to 2\n",
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+ __FUNCTION__);
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+ }
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+
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+ return 2;
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+}
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+
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static inline void write_tmr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
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