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@@ -1593,10 +1593,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
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(power_state->ucNonClockStateIndex *
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power_info->info_4.ucNonClockSize));
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- misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
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- rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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- ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
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- ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
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for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
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if (rdev->flags & RADEON_IS_IGP) {
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struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
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@@ -1654,7 +1650,11 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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}
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rdev->pm.power_state[state_index].num_clock_modes = mode_index;
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if (mode_index) {
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+ misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
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misc2 = le16_to_cpu(non_clock_info->usClassification);
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+ rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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+ ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
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+ ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
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if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
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rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
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rdev->pm.current_power_state = &rdev->pm.power_state[state_index];
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