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@@ -72,6 +72,7 @@
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#define MXS_I2C_QUEUESTAT (0x70)
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#define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
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+#define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F
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#define MXS_I2C_QUEUECMD (0x80)
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@@ -219,14 +220,14 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
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int ret;
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int flags;
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- init_completion(&i2c->cmd_complete);
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-
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dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
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msg->addr, msg->len, msg->flags, stop);
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if (msg->len == 0)
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return -EINVAL;
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+ init_completion(&i2c->cmd_complete);
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+
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flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
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if (msg->flags & I2C_M_RD)
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@@ -286,6 +287,7 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
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{
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struct mxs_i2c_dev *i2c = dev_id;
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u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
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+ bool is_last_cmd;
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if (!stat)
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return IRQ_NONE;
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@@ -300,9 +302,14 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
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else
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i2c->cmd_err = 0;
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- complete(&i2c->cmd_complete);
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+ is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
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+ MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
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+
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+ if (is_last_cmd || i2c->cmd_err)
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+ complete(&i2c->cmd_complete);
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writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
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+
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return IRQ_HANDLED;
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}
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