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@@ -50,6 +50,7 @@
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#define CR_920T_ASYNC_MODE 0xC0000000
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static u32 mpctl0_at_boot;
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+static u32 bclk_div_at_boot;
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static void imx_set_async_mode(void)
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{
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@@ -182,7 +183,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
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unsigned long flags;
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long freq;
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long sysclk;
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- unsigned int bclk_div = 1;
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+ unsigned int bclk_div = bclk_div_at_boot;
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/*
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* Some governors do not respects CPU and policy lower limits
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@@ -202,7 +203,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
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sysclk = imx_get_system_clk();
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- if (freq > sysclk + 1000000) {
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+ if (freq > sysclk / bclk_div_at_boot + 1000000) {
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freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
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if (freq < 0) {
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printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
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@@ -217,6 +218,8 @@ static int imx_set_target(struct cpufreq_policy *policy,
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if(bclk_div > 16)
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bclk_div = 16;
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+ if(bclk_div < bclk_div_at_boot)
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+ bclk_div = bclk_div_at_boot;
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}
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freq = (sysclk + bclk_div / 2) / bclk_div;
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}
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@@ -285,7 +288,7 @@ static struct cpufreq_driver imx_driver = {
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static int __init imx_cpufreq_init(void)
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{
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-
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+ bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
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mpctl0_at_boot = 0;
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if((CSCR & CSCR_MPEN) &&
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