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@@ -12,6 +12,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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+#include <linux/mbus.h>
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#include <asm/hardware.h>
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#include "common.h"
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@@ -168,6 +169,9 @@
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#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
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#define SATA_MAX_WIN 4
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+
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+struct mbus_dram_target_info orion_mbus_dram_info;
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+
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static int __init orion_cpu_win_can_remap(u32 win)
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{
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u32 dev, rev;
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@@ -257,6 +261,7 @@ void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, in
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void __init orion_setup_cpu_wins(void)
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{
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int i;
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+ int cs;
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/*
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* First, disable and clear windows
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@@ -281,6 +286,30 @@ void __init orion_setup_cpu_wins(void)
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ORION_PCIE_MEM_SIZE, -1);
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orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
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ORION_PCI_MEM_SIZE, -1);
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+
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+ /*
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+ * Setup MBUS dram target info.
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+ */
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+ orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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+
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+ for (i = 0, cs = 0; i < 4; i++) {
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+ u32 base = readl(DDR_BASE_CS(i));
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+ u32 size = readl(DDR_SIZE_CS(i));
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+
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+ /*
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+ * Chip select enabled?
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+ */
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+ if (size & 1) {
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+ struct mbus_dram_window *w;
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+
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+ w = &orion_mbus_dram_info.cs[cs++];
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+ w->cs_index = i;
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+ w->mbus_attr = 0xf & ~(1 << i);
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+ w->base = base & 0xff000000;
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+ w->size = (size | 0x00ffffff) + 1;
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+ }
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+ }
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+ orion_mbus_dram_info.num_cs = cs;
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}
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/*
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