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@@ -129,7 +129,6 @@ enum imxdma_prep_type {
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*/
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struct imxdma_channel_internal {
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- struct scatterlist *sg;
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unsigned int resbytes;
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int in_use;
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@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
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CCR_ACRPT, DMA_CCR(channel));
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if ((cpu_is_mx21() || cpu_is_mx27()) &&
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- imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
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- imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
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- if (imxdmac->internal.sg) {
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+ d->sg && imxdma_hw_chain(&imxdmac->internal)) {
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+ d->sg = sg_next(d->sg);
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+ if (d->sg) {
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u32 tmp;
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- imxdma_sg_next(d, imxdmac->internal.sg);
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+ imxdma_sg_next(d, d->sg);
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tmp = imx_dmav1_readl(DMA_CCR(channel));
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imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
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imx_dmav1_writel(0, DMA_CCR(channel));
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imxdmac->internal.in_use = 0;
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- imxdmac->internal.sg = NULL;
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/* Tasklet watchdog error handler */
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tasklet_schedule(&imxdmac->dma_tasklet);
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@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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int chno = imxdmac->channel;
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struct imxdma_desc *desc;
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- if (imxdma->sg) {
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- u32 tmp;
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- imxdma->sg = sg_next(imxdma->sg);
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-
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- if (imxdma->sg) {
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+ spin_lock(&imxdmac->lock);
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+ if (list_empty(&imxdmac->ld_active)) {
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+ spin_unlock(&imxdmac->lock);
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+ goto out;
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+ }
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- spin_lock(&imxdmac->lock);
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- if (list_empty(&imxdmac->ld_active)) {
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- spin_unlock(&imxdmac->lock);
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- goto out;
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- }
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+ desc = list_first_entry(&imxdmac->ld_active,
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+ struct imxdma_desc,
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+ node);
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+ spin_unlock(&imxdmac->lock);
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- desc = list_first_entry(&imxdmac->ld_active,
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- struct imxdma_desc,
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- node);
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- spin_unlock(&imxdmac->lock);
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+ if (desc->sg) {
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+ u32 tmp;
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+ desc->sg = sg_next(desc->sg);
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- imxdma_sg_next(desc, imxdma->sg);
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+ if (desc->sg) {
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+ imxdma_sg_next(desc, desc->sg);
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tmp = imx_dmav1_readl(DMA_CCR(chno));
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@@ -477,8 +474,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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/* Configure and enable */
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switch (d->type) {
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case IMXDMA_DESC_MEMCPY:
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- imxdmac->internal.sg = NULL;
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-
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imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
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imx_dmav1_writel(d->config_mem | (d->config_port << 2),
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@@ -494,7 +489,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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/* Cyclic transfer is the same as slave_sg with special sg configuration. */
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case IMXDMA_DESC_CYCLIC:
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case IMXDMA_DESC_SLAVE_SG:
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- imxdmac->internal.sg = d->sg;
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imxdmac->internal.resbytes = d->len;
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if (d->direction == DMA_DEV_TO_MEM) {
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