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@@ -1,4 +1,4 @@
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-/* linux/arch/arm/mach-exynos4/cpu.c
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+/* linux/arch/arm/mach-exynos/cpu.c
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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@@ -40,27 +40,46 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
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extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
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/* Initial IO mappings */
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-static struct map_desc exynos4_iodesc[] __initdata = {
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+static struct map_desc exynos_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
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+ .pfn = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
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.length = SZ_4K,
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- .type = MT_DEVICE,
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- }, {
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- .virtual = (unsigned long)S5P_VA_CMU,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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- .length = SZ_128K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
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+ .pfn = __phys_to_pfn(EXYNOS_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
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+ .pfn = __phys_to_pfn(EXYNOS_PA_COMBINER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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+ }, {
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+ .virtual = (unsigned long)S5P_VA_GIC_CPU,
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+ .pfn = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
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+ .length = SZ_64K,
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+ .type = MT_DEVICE,
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+ }, {
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+ .virtual = (unsigned long)S5P_VA_GIC_DIST,
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+ .pfn = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
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+ .length = SZ_64K,
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+ .type = MT_DEVICE,
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+ }, {
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+ .virtual = (unsigned long)S3C_VA_UART,
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+ .pfn = __phys_to_pfn(S3C_PA_UART),
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+ .length = SZ_512K,
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+ .type = MT_DEVICE,
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+ },
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+};
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+
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+static struct map_desc exynos4_iodesc[] __initdata = {
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+ {
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+ .virtual = (unsigned long)S5P_VA_CMU,
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+ .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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+ .length = SZ_128K,
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+ .type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
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@@ -91,11 +110,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
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.length = SZ_4K,
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.type = MT_DEVICE,
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- }, {
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- .virtual = (unsigned long)S3C_VA_UART,
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- .pfn = __phys_to_pfn(S3C_PA_UART),
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- .length = SZ_512K,
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- .type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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@@ -106,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
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.length = SZ_4K,
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.type = MT_DEVICE,
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- }, {
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- .virtual = (unsigned long)S5P_VA_GIC_CPU,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
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- .length = SZ_64K,
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- .type = MT_DEVICE,
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- }, {
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- .virtual = (unsigned long)S5P_VA_GIC_DIST,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
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- .length = SZ_64K,
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- .type = MT_DEVICE,
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},
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};
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@@ -137,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
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},
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};
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-static void exynos4_idle(void)
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+static void exynos_idle(void)
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{
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if (!need_resched())
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cpu_do_idle();
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@@ -151,12 +155,13 @@ static void exynos4_sw_reset(void)
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}
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/*
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- * exynos4_map_io
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+ * exynos_map_io
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*
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* register the standard cpu IO areas
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*/
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void __init exynos4_map_io(void)
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{
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+ iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
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@@ -250,7 +255,6 @@ static int __init exynos4_core_init(void)
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{
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return sysdev_class_register(&exynos4_sysclass);
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}
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-
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core_initcall(exynos4_core_init);
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#ifdef CONFIG_CACHE_L2X0
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@@ -279,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void)
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early_initcall(exynos4_l2x0_cache_init);
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#endif
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-int __init exynos4_init(void)
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+int __init exynos_init(void)
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{
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- printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
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+ printk(KERN_INFO "EXYNOS: Initializing architecture\n");
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/* set idle function */
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- pm_idle = exynos4_idle;
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+ pm_idle = exynos_idle;
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/* set sw_reset function */
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- s5p_reset_hook = exynos4_sw_reset;
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+ if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
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+ s5p_reset_hook = exynos4_sw_reset;
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return sysdev_register(&exynos4_sysdev);
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}
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