|
@@ -2789,6 +2789,47 @@ void si_vm_fini(struct radeon_device *rdev)
|
|
{
|
|
{
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+/**
|
|
|
|
+ * si_vm_set_page - update the page tables using the CP
|
|
|
|
+ *
|
|
|
|
+ * @rdev: radeon_device pointer
|
|
|
|
+ * @pe: addr of the page entry
|
|
|
|
+ * @addr: dst addr to write into pe
|
|
|
|
+ * @count: number of page entries to update
|
|
|
|
+ * @incr: increase next addr by incr bytes
|
|
|
|
+ * @flags: access flags
|
|
|
|
+ *
|
|
|
|
+ * Update the page tables using the CP (cayman-si).
|
|
|
|
+ */
|
|
|
|
+void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
|
|
|
|
+ uint64_t addr, unsigned count,
|
|
|
|
+ uint32_t incr, uint32_t flags)
|
|
|
|
+{
|
|
|
|
+ struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
|
|
|
|
+ uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
|
|
|
|
+ int i;
|
|
|
|
+ uint64_t value;
|
|
|
|
+
|
|
|
|
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 2 + count * 2));
|
|
|
|
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
|
|
|
+ WRITE_DATA_DST_SEL(1)));
|
|
|
|
+ radeon_ring_write(ring, pe);
|
|
|
|
+ radeon_ring_write(ring, upper_32_bits(pe));
|
|
|
|
+ for (i = 0; i < count; ++i) {
|
|
|
|
+ if (flags & RADEON_VM_PAGE_SYSTEM) {
|
|
|
|
+ value = radeon_vm_map_gart(rdev, addr);
|
|
|
|
+ value &= 0xFFFFFFFFFFFFF000ULL;
|
|
|
|
+ } else if (flags & RADEON_VM_PAGE_VALID)
|
|
|
|
+ value = addr;
|
|
|
|
+ else
|
|
|
|
+ value = 0;
|
|
|
|
+ addr += incr;
|
|
|
|
+ value |= r600_flags;
|
|
|
|
+ radeon_ring_write(ring, value);
|
|
|
|
+ radeon_ring_write(ring, upper_32_bits(value));
|
|
|
|
+ }
|
|
|
|
+}
|
|
|
|
+
|
|
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|
{
|
|
{
|
|
struct radeon_ring *ring = &rdev->ring[ridx];
|
|
struct radeon_ring *ring = &rdev->ring[ridx];
|