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@@ -0,0 +1,15 @@
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+#ifndef _UAPI_METAG_ECH_H
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+#define _UAPI_METAG_ECH_H
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+
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+/*
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+ * These bits can be set in the top half of the D0.8 register when DSP context
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+ * switching is enabled, in order to support partial DSP context save/restore.
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+ */
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+
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+#define TBICTX_XEXT_BIT 0x1000 /* Enable extended context save */
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+#define TBICTX_XTDP_BIT 0x0800 /* DSP accumulators/RAM/templates */
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+#define TBICTX_XHL2_BIT 0x0400 /* Hardware loops */
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+#define TBICTX_XAXX_BIT 0x0200 /* Extended AX registers (A*.4-7) */
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+#define TBICTX_XDX8_BIT 0x0100 /* Extended DX registers (D*.8-15) */
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+
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+#endif /* _UAPI_METAG_ECH_H */
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