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@@ -2351,7 +2351,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
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- u32 error_mask;
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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@@ -2372,16 +2371,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
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* Enable some error detection, note the instruction error mask
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* bit is reserved, so we leave it masked.
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*/
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- if (IS_G4X(dev)) {
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- error_mask = ~(GM45_ERROR_PAGE_TABLE |
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- GM45_ERROR_MEM_PRIV |
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- GM45_ERROR_CP_PRIV |
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- I915_ERROR_MEMORY_REFRESH);
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- } else {
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- error_mask = ~(I915_ERROR_PAGE_TABLE |
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- I915_ERROR_MEMORY_REFRESH);
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- }
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- I915_WRITE(EMR, error_mask);
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+ I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
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I915_WRITE(IMR, dev_priv->irq_mask);
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I915_WRITE(IER, enable_mask);
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@@ -2390,7 +2380,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
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if (I915_HAS_HOTPLUG(dev)) {
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u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
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- /* Note HDMI and DP share bits */
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if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMIB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
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@@ -2403,13 +2392,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
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hotplug_en |= SDVOB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
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hotplug_en |= CRT_HOTPLUG_INT_EN;
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-
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- /* Programming the CRT detection parameters tends
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- to generate a spurious hotplug event about three
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- seconds later. So just do it once.
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- */
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- if (IS_G4X(dev))
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- hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
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hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
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}
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@@ -2428,26 +2410,17 @@ static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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struct drm_i915_master_private *master_priv;
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- u32 iir, new_iir;
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- u32 pipe_stats[I915_MAX_PIPES];
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- u32 vblank_status;
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- int vblank = 0;
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+ u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
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unsigned long irqflags;
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- int irq_received;
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int ret = IRQ_NONE, pipe;
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- bool blc_event = false;
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atomic_inc(&dev_priv->irq_received);
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iir = I915_READ(IIR);
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- if (INTEL_INFO(dev)->gen >= 4)
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- vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
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- else
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- vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
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-
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for (;;) {
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- irq_received = iir != 0;
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+ bool blc_event = false;
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+ int irq_received = iir != 0;
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/* Can't rely on pipestat interrupt bit in iir as it might
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* have been cleared after the pipestat interrupt was received.
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@@ -2498,17 +2471,8 @@ static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
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I915_WRITE(IIR, iir);
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new_iir = I915_READ(IIR); /* Flush posted writes */
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- if (dev->primary->master) {
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- master_priv = dev->primary->master->driver_priv;
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- if (master_priv->sarea_priv)
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- master_priv->sarea_priv->last_dispatch =
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- READ_BREADCRUMB(dev_priv);
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- }
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-
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if (iir & I915_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[RCS]);
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- if (iir & I915_BSD_USER_INTERRUPT)
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- notify_ring(dev, &dev_priv->ring[VCS]);
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if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
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intel_prepare_page_flip(dev, 0);
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@@ -2517,9 +2481,8 @@ static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
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intel_prepare_page_flip(dev, 1);
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for_each_pipe(pipe) {
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- if (pipe_stats[pipe] & vblank_status &&
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+ if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
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drm_handle_vblank(dev, pipe)) {
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- vblank++;
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i915_pageflip_stall_check(dev, pipe);
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intel_finish_page_flip(dev, pipe);
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}
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@@ -2528,7 +2491,6 @@ static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
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blc_event = true;
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}
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-
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if (blc_event || (iir & I915_ASLE_INTERRUPT))
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intel_opregion_asle_intr(dev);
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@@ -2550,6 +2512,13 @@ static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
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iir = new_iir;
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}
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+ if (dev->primary->master) {
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+ master_priv = dev->primary->master->driver_priv;
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+ if (master_priv->sarea_priv)
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+ master_priv->sarea_priv->last_dispatch =
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+ READ_BREADCRUMB(dev_priv);
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+ }
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+
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return ret;
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}
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