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@@ -14,7 +14,6 @@
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*/
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#include <linux/err.h>
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-#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@@ -29,16 +28,6 @@
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#define DRIVER_NAME "spear-pinmux"
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-static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
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-{
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- return readl_relaxed(pmx->vbase + reg);
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-}
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-
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-static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
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-{
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- writel_relaxed(val, pmx->vbase + reg);
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-}
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-
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static void muxregs_endisable(struct spear_pmx *pmx,
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struct spear_muxreg *muxregs, u8 count, bool enable)
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{
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@@ -316,16 +305,25 @@ static int gpio_request_endisable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset, bool enable)
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{
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struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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+ struct spear_pinctrl_machdata *machdata = pmx->machdata;
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struct spear_gpio_pingroup *gpio_pingroup;
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+ /*
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+ * Some SoC have configuration options applicable to group of pins,
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+ * rather than a single pin.
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+ */
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gpio_pingroup = get_gpio_pingroup(pmx, offset);
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- if (IS_ERR(gpio_pingroup))
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- return PTR_ERR(gpio_pingroup);
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-
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if (gpio_pingroup)
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muxregs_endisable(pmx, gpio_pingroup->muxregs,
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gpio_pingroup->nmuxregs, enable);
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+ /*
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+ * SoC may need some extra configurations, or configurations for single
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+ * pin
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+ */
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+ if (machdata->gpio_request_endisable)
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+ machdata->gpio_request_endisable(pmx, offset, enable);
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+
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return 0;
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}
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