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@@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata;
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static struct uasm_label labels[128] __cpuinitdata;
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static struct uasm_reloc relocs[128] __cpuinitdata;
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+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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+/*
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+ * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
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+ * we cannot do r3000 under these circumstances.
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+ */
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+
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/*
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* The R3000 TLB handler is simple.
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*/
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@@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
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dump_handler((u32 *)ebase, 32);
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}
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+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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/*
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* The R4000 TLB handler is much more complicated. We have two
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@@ -497,8 +504,9 @@ static void __cpuinit
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build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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unsigned int tmp, unsigned int ptr)
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{
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+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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long pgdc = (long)pgd_current;
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-
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+#endif
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/*
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* The vmalloc handling is not in the hotpath.
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*/
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@@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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uasm_il_bltz(p, r, tmp, label_vmalloc);
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/* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
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-#ifdef CONFIG_SMP
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+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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+ /*
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+ * &pgd << 11 stored in CONTEXT [23..63].
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+ */
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+ UASM_i_MFC0(p, ptr, C0_CONTEXT);
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+ uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
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+ uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
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+ uasm_i_drotr(p, ptr, ptr, 11);
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+#elif defined(CONFIG_SMP)
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# ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC uses TCBind value as "CPU" index
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@@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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*/
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uasm_i_dmfc0(p, ptr, C0_CONTEXT);
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uasm_i_dsrl(p, ptr, ptr, 23);
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-#endif
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+# endif
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UASM_i_LA_mostly(p, tmp, pgdc);
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uasm_i_daddu(p, ptr, ptr, tmp);
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uasm_i_dmfc0(p, tmp, C0_BADVADDR);
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@@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
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iPTE_LW(p, pte, ptr);
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}
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+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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/*
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* R3000 style TLB load/store/modify handlers.
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*/
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@@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
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dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
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}
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+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
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/*
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* R4000 style TLB load/store/modify handlers.
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@@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void)
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case CPU_TX3912:
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case CPU_TX3922:
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case CPU_TX3927:
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+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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build_r3000_tlb_refill_handler();
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if (!run_once) {
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build_r3000_tlb_load_handler();
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@@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void)
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build_r3000_tlb_modify_handler();
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run_once++;
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}
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+#else
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+ panic("No R3000 TLB refill handler");
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+#endif
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break;
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case CPU_R6000:
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