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@@ -24,15 +24,17 @@
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#include <linux/of.h>
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/* Clock Manager offsets */
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-#define CLKMGR_CTRL 0x0
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-#define CLKMGR_BYPASS 0x4
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+#define CLKMGR_CTRL 0x0
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+#define CLKMGR_BYPASS 0x4
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+#define CLKMGR_L4SRC 0x70
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+#define CLKMGR_PERPLL_SRC 0xAC
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/* Clock bypass bits */
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-#define MAINPLL_BYPASS (1<<0)
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-#define SDRAMPLL_BYPASS (1<<1)
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-#define SDRAMPLL_SRC_BYPASS (1<<2)
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-#define PERPLL_BYPASS (1<<3)
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-#define PERPLL_SRC_BYPASS (1<<4)
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+#define MAINPLL_BYPASS (1<<0)
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+#define SDRAMPLL_BYPASS (1<<1)
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+#define SDRAMPLL_SRC_BYPASS (1<<2)
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+#define PERPLL_BYPASS (1<<3)
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+#define PERPLL_SRC_BYPASS (1<<4)
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#define SOCFPGA_PLL_BG_PWRDWN 0
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#define SOCFPGA_PLL_EXT_ENA 1
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@@ -41,6 +43,17 @@
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#define SOCFPGA_PLL_DIVF_SHIFT 3
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#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
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#define SOCFPGA_PLL_DIVQ_SHIFT 16
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+#define SOCFGPA_MAX_PARENTS 3
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+
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+#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
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+#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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+#define SOCFPGA_NAND_CLK "nand_clk"
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+#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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+#define SOCFPGA_MMC_CLK "mmc_clk"
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+#define SOCFPGA_DB_CLK "gpio_db_clk"
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+
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+#define div_mask(width) ((1 << (width)) - 1)
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+#define streq(a, b) (strcmp((a), (b)) == 0)
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extern void __iomem *clk_mgr_base_addr;
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@@ -49,6 +62,9 @@ struct socfpga_clk {
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char *parent_name;
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char *clk_name;
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u32 fixed_div;
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+ void __iomem *div_reg;
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+ u32 width; /* only valid if div_reg != 0 */
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+ u32 shift; /* only valid if div_reg != 0 */
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};
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#define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
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@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
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socfpga_clk->hw.hw.init = &init;
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- if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
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- strcmp(clk_name, "sdram_pll")) {
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+ if (streq(clk_name, "main_pll") ||
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+ streq(clk_name, "periph_pll") ||
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+ streq(clk_name, "sdram_pll")) {
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socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
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return clk;
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}
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+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
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+{
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+ u32 l4_src;
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+ u32 perpll_src;
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+
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+ if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
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+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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+ return l4_src &= 0x1;
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+ }
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+ if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
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+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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+ return !!(l4_src & 2);
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+ }
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+
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+ perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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+ if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
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+ return perpll_src &= 0x3;
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+ if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
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+ streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
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+ return (perpll_src >> 2) & 3;
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+
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+ /* QSPI clock */
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+ return (perpll_src >> 4) & 3;
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+
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+}
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+
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+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
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+{
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+ u32 src_reg;
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+
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+ if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
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+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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+ src_reg &= ~0x1;
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+ src_reg |= parent;
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+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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+ } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
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+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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+ src_reg &= ~0x2;
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+ src_reg |= (parent << 1);
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+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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+ } else {
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+ src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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+ if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
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+ src_reg &= ~0x3;
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+ src_reg |= parent;
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+ } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
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+ streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
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+ src_reg &= ~0xC;
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+ src_reg |= (parent << 2);
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+ } else {/* QSPI clock */
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+ src_reg &= ~0x30;
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+ src_reg |= (parent << 4);
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+ }
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+ writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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+ }
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+
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+ return 0;
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+}
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+
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+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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+ unsigned long parent_rate)
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+{
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+ struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
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+ u32 div = 1, val;
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+
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+ if (socfpgaclk->fixed_div)
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+ div = socfpgaclk->fixed_div;
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+ else if (socfpgaclk->div_reg) {
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+ val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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+ val &= div_mask(socfpgaclk->width);
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+ if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
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+ div = val + 1;
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+ else
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+ div = (1 << val);
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+ }
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+
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+ return parent_rate / div;
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+}
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+
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+static struct clk_ops gateclk_ops = {
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+ .recalc_rate = socfpga_clk_recalc_rate,
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+ .get_parent = socfpga_clk_get_parent,
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+ .set_parent = socfpga_clk_set_parent,
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+};
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+
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+static void __init socfpga_gate_clk_init(struct device_node *node,
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+ const struct clk_ops *ops)
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+{
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+ u32 clk_gate[2];
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+ u32 div_reg[3];
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+ u32 fixed_div;
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+ struct clk *clk;
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+ struct socfpga_clk *socfpga_clk;
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+ const char *clk_name = node->name;
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+ const char *parent_name[SOCFGPA_MAX_PARENTS];
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+ struct clk_init_data init;
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+ int rc;
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+ int i = 0;
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+
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+ socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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+ if (WARN_ON(!socfpga_clk))
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+ return;
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+
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+ rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
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+ if (rc)
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+ clk_gate[0] = 0;
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+
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+ if (clk_gate[0]) {
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+ socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
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+ socfpga_clk->hw.bit_idx = clk_gate[1];
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+
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+ gateclk_ops.enable = clk_gate_ops.enable;
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+ gateclk_ops.disable = clk_gate_ops.disable;
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+ }
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+
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+ rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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+ if (rc)
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+ socfpga_clk->fixed_div = 0;
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+ else
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+ socfpga_clk->fixed_div = fixed_div;
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+
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+ rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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+ if (!rc) {
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+ socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
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+ socfpga_clk->shift = div_reg[1];
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+ socfpga_clk->width = div_reg[2];
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+ } else {
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+ socfpga_clk->div_reg = 0;
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+ }
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+
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+ of_property_read_string(node, "clock-output-names", &clk_name);
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+
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+ init.name = clk_name;
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+ init.ops = ops;
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+ init.flags = 0;
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+ while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
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+ of_clk_get_parent_name(node, i)) != NULL)
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+ i++;
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+
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+ init.parent_names = parent_name;
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+ init.num_parents = i;
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+ socfpga_clk->hw.hw.init = &init;
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+
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+ clk = clk_register(NULL, &socfpga_clk->hw.hw);
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+ if (WARN_ON(IS_ERR(clk))) {
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+ kfree(socfpga_clk);
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+ return;
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+ }
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+ rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ if (WARN_ON(rc))
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+ return;
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+}
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+
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static void __init socfpga_pll_init(struct device_node *node)
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{
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socfpga_clk_init(node, &clk_pll_ops);
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@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
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}
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CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
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+static void __init socfpga_gate_init(struct device_node *node)
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+{
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+ socfpga_gate_clk_init(node, &gateclk_ops);
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+}
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+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
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+
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void __init socfpga_init_clocks(void)
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{
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struct clk *clk;
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