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@@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd)
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/* Early initializations */
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void __init versatile_init_early(void)
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{
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+ u32 val;
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void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
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osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
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+
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+ /*
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+ * set clock frequency:
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+ * VERSATILE_REFCLK is 32KHz
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+ * VERSATILE_TIMCLK is 1MHz
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+ */
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+ val = readl(__io_address(VERSATILE_SCTL_BASE));
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+ writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
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+ (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
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+ (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
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+ (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
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+ __io_address(VERSATILE_SCTL_BASE));
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}
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void __init versatile_init(void)
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@@ -785,19 +798,6 @@ void __init versatile_init(void)
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*/
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void __init versatile_timer_init(void)
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{
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- u32 val;
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-
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- /*
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- * set clock frequency:
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- * VERSATILE_REFCLK is 32KHz
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- * VERSATILE_TIMCLK is 1MHz
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- */
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- val = readl(__io_address(VERSATILE_SCTL_BASE));
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- writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
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- (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
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- (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
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- (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
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- __io_address(VERSATILE_SCTL_BASE));
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/*
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* Initialise to a known state (all timers off)
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