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@@ -30,7 +30,7 @@ volatile int __cpuinitdata pen_release = -1;
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static unsigned int __init get_core_count(void)
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{
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- return scu_get_core_count(__io_address(U8500_SCU_BASE));
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+ return scu_get_core_count(__io_address(UX500_SCU_BASE));
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}
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static DEFINE_SPINLOCK(boot_lock);
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@@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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- gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
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+ gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
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/*
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* let the primary processor know we're out of the
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@@ -106,12 +106,12 @@ static void __init wakeup_secondary(void)
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*/
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#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
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__raw_writel(virt_to_phys(u8500_secondary_startup),
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- (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
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+ __io_address(UX500_BACKUPRAM0_BASE) +
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U8500_CPU1_JUMPADDR_OFFSET);
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#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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__raw_writel(0xA1FEED01,
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- (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
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+ __io_address(UX500_BACKUPRAM0_BASE) +
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U8500_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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@@ -172,7 +172,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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* boot CPU, but only if we have more than one CPU.
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*/
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percpu_timer_setup();
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- scu_enable(__io_address(U8500_SCU_BASE));
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+ scu_enable(__io_address(UX500_SCU_BASE));
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wakeup_secondary();
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}
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}
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