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@@ -27,13 +27,6 @@
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#include <linux/slab.h>
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#include <linux/slab.h>
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-#define DEBUG_CONFIG 1
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-#if DEBUG_CONFIG
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-#define DBG(x...) printk(x)
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-#else
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-#define DBG(x...)
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-#endif
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-
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static void pbus_assign_resources_sorted(struct pci_bus *bus)
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static void pbus_assign_resources_sorted(struct pci_bus *bus)
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{
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{
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struct pci_dev *dev;
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struct pci_dev *dev;
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@@ -81,8 +74,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
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struct pci_dev *bridge = bus->self;
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struct pci_dev *bridge = bus->self;
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struct pci_bus_region region;
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struct pci_bus_region region;
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- printk("PCI: Bus %d, cardbus bridge: %s\n",
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- bus->number, pci_name(bridge));
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+ dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
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+ pci_domain_nr(bus), bus->number);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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if (bus->resource[0]->flags & IORESOURCE_IO) {
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if (bus->resource[0]->flags & IORESOURCE_IO) {
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@@ -90,7 +83,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
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* The IO resource is allocated a range twice as large as it
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* The IO resource is allocated a range twice as large as it
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* would normally need. This allows us to set both IO regs.
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* would normally need. This allows us to set both IO regs.
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*/
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*/
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- printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
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+ dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
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@@ -101,7 +94,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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if (bus->resource[1]->flags & IORESOURCE_IO) {
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if (bus->resource[1]->flags & IORESOURCE_IO) {
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- printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
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+ dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
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@@ -112,7 +105,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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if (bus->resource[2]->flags & IORESOURCE_MEM) {
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if (bus->resource[2]->flags & IORESOURCE_MEM) {
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- printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n",
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+ dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
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@@ -123,7 +116,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
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if (bus->resource[3]->flags & IORESOURCE_MEM) {
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if (bus->resource[3]->flags & IORESOURCE_MEM) {
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- printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
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+ dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
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@@ -151,7 +144,8 @@ static void pci_setup_bridge(struct pci_bus *bus)
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struct pci_bus_region region;
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struct pci_bus_region region;
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u32 l, bu, lu, io_upper16;
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u32 l, bu, lu, io_upper16;
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- DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
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+ dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
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+ pci_domain_nr(bus), bus->number);
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/* Set up the top and bottom of the PCI I/O segment for this bus. */
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/* Set up the top and bottom of the PCI I/O segment for this bus. */
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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@@ -162,7 +156,7 @@ static void pci_setup_bridge(struct pci_bus *bus)
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l |= region.end & 0xf000;
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l |= region.end & 0xf000;
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/* Set up upper 16 bits of I/O base/limit. */
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/* Set up upper 16 bits of I/O base/limit. */
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io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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- DBG(KERN_INFO " IO window: %04lx-%04lx\n",
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+ dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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}
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}
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@@ -170,7 +164,7 @@ static void pci_setup_bridge(struct pci_bus *bus)
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/* Clear upper 16 bits of I/O base/limit. */
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/* Clear upper 16 bits of I/O base/limit. */
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io_upper16 = 0;
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io_upper16 = 0;
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l = 0x00f0;
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l = 0x00f0;
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- DBG(KERN_INFO " IO window: disabled.\n");
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+ dev_info(&bridge->dev, " IO window: disabled\n");
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}
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}
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/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
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/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
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@@ -185,13 +179,13 @@ static void pci_setup_bridge(struct pci_bus *bus)
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if (bus->resource[1]->flags & IORESOURCE_MEM) {
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if (bus->resource[1]->flags & IORESOURCE_MEM) {
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l = (region.start >> 16) & 0xfff0;
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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l |= region.end & 0xfff00000;
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- DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
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+ dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.start,
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(unsigned long)region.end);
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(unsigned long)region.end);
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}
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}
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else {
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else {
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l = 0x0000fff0;
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l = 0x0000fff0;
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- DBG(KERN_INFO " MEM window: disabled.\n");
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+ dev_info(&bridge->dev, " MEM window: disabled\n");
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}
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}
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pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
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pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
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@@ -208,13 +202,13 @@ static void pci_setup_bridge(struct pci_bus *bus)
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l |= region.end & 0xfff00000;
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l |= region.end & 0xfff00000;
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bu = upper_32_bits(region.start);
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bu = upper_32_bits(region.start);
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lu = upper_32_bits(region.end);
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lu = upper_32_bits(region.end);
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- DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n",
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+ dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n",
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(unsigned long long)region.start,
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(unsigned long long)region.start,
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(unsigned long long)region.end);
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(unsigned long long)region.end);
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}
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}
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else {
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else {
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l = 0x0000fff0;
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l = 0x0000fff0;
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- DBG(KERN_INFO " PREFETCH window: disabled.\n");
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+ dev_info(&bridge->dev, " PREFETCH window: disabled\n");
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}
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}
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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@@ -361,9 +355,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
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align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
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align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
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order = __ffs(align) - 20;
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order = __ffs(align) - 20;
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if (order > 11) {
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if (order > 11) {
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- printk(KERN_WARNING "PCI: region %s/%d "
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- "too large: 0x%016llx-0x%016llx\n",
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- pci_name(dev), i,
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+ dev_warn(&dev->dev, "BAR %d too large: "
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+ "%#016llx-%#016llx\n", i,
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(unsigned long long)r->start,
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(unsigned long long)r->start,
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(unsigned long long)r->end);
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(unsigned long long)r->end);
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r->flags = 0;
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r->flags = 0;
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@@ -529,8 +522,8 @@ void __ref pci_bus_assign_resources(struct pci_bus *bus)
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break;
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break;
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default:
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default:
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- printk(KERN_INFO "PCI: not setting up bridge %s "
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- "for bus %d\n", pci_name(dev), b->number);
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+ dev_info(&dev->dev, "not setting up bridge for bus "
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+ "%04x:%02x\n", pci_domain_nr(b), b->number);
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break;
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break;
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}
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}
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}
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}
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