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@@ -92,7 +92,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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-.equ cpu_v7_suspend_size, 4 * 8
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+.equ cpu_v7_suspend_size, 4 * 9
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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@@ -101,13 +101,17 @@ ENTRY(cpu_v7_do_suspend)
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stmia r0!, {r4 - r5}
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#ifdef CONFIG_MMU
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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+#ifdef CONFIG_ARM_LPAE
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+ mrrc p15, 1, r5, r7, c2 @ TTB 1
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+#else
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mrc p15, 0, r7, c2, c0, 1 @ TTB 1
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+#endif
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mrc p15, 0, r11, c2, c0, 2 @ TTB control register
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#endif
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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- stmia r0, {r6 - r11}
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+ stmia r0, {r5 - r11}
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ldmfd sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)
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@@ -118,16 +122,19 @@ ENTRY(cpu_v7_do_resume)
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ldmia r0!, {r4 - r5}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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- ldmia r0, {r6 - r11}
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+ ldmia r0, {r5 - r11}
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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-#ifndef CONFIG_ARM_LPAE
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+#ifdef CONFIG_ARM_LPAE
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+ mcrr p15, 0, r1, ip, c2 @ TTB 0
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+ mcrr p15, 1, r5, r7, c2 @ TTB 1
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+#else
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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-#endif
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mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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+#endif
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mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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