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@@ -0,0 +1,33 @@
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+ .macro bitop, instr
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+ and r2, r0, #7
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+ mov r3, #1
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+ mov r3, r3, lsl r2
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+ save_and_disable_irqs ip, r2
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+ ldrb r2, [r1, r0, lsr #3]
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+ \instr r2, r2, r3
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+ strb r2, [r1, r0, lsr #3]
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+ restore_irqs ip
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+ mov pc, lr
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+ .endm
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+
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+/**
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+ * testop - implement a test_and_xxx_bit operation.
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+ * @instr: operational instruction
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+ * @store: store instruction
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+ *
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+ * Note: we can trivially conditionalise the store instruction
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+ * to avoid dirting the data cache.
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+ */
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+ .macro testop, instr, store
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+ add r1, r1, r0, lsr #3
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+ and r3, r0, #7
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+ mov r0, #1
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+ save_and_disable_irqs ip, r2
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+ ldrb r2, [r1]
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+ tst r2, r0, lsl r3
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+ \instr r2, r2, r0, lsl r3
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+ \store r2, [r1]
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+ restore_irqs ip
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+ moveq r0, #0
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+ mov pc, lr
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+ .endm
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