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@@ -3796,13 +3796,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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POSTING_READ(PCH_DREF_CONTROL);
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udelay(200);
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+ }
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+ temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
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- temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
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- temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
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+ /* Enable CPU source on CPU attached eDP */
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+ if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
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+ if (dev_priv->lvds_use_ssc)
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+ temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
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+ else
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+ temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
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} else {
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- temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
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+ /* Enable SSC on PCH eDP if needed */
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+ if (dev_priv->lvds_use_ssc) {
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+ DRM_ERROR("enabling SSC on PCH\n");
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+ temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
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+ }
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}
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I915_WRITE(PCH_DREF_CONTROL, temp);
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+ POSTING_READ(PCH_DREF_CONTROL);
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+ udelay(200);
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}
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}
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