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@@ -41,12 +41,14 @@ enum GPIO_REG {
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GPIO_USE_SEL = 0,
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GPIO_IO_SEL,
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GPIO_LVL,
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+ GPO_BLINK
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};
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-static const u8 ichx_regs[3][3] = {
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+static const u8 ichx_regs[4][3] = {
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{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
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{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
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{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
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+ {0x18, 0x18, 0x18}, /* BLINK offset */
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};
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static const u8 ichx_reglen[3] = {
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@@ -148,6 +150,10 @@ static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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{
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+ /* Disable blink hardware which is available for GPIOs from 0 to 31. */
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+ if (nr < 32)
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+ ichx_write_bit(GPO_BLINK, nr, 0, 0);
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+
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/* Set GPIO output value. */
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ichx_write_bit(GPIO_LVL, nr, val, 0);
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