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@@ -44,6 +44,8 @@
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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+#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
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+
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#define ACTIVE_DOORBELLS (8)
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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@@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
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#ifdef CONFIG_SMP
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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- if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
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+ if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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@@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
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#ifdef CONFIG_SMP
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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- if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
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+ if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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@@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_status_flags(virq, IRQ_LEVEL);
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- if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
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+ if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
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irq_set_percpu_devid(virq);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_percpu_devid_irq);
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