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@@ -376,13 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R4000PC";
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}
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} else {
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+ int cca = read_c0_config() & CONF_CM_CMASK;
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+ int mc;
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+
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+ /*
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+ * SC and MC versions can't be reliably told apart,
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+ * but only the latter support coherent caching
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+ * modes so assume the firmware has set the KSEG0
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+ * coherency attribute reasonably (if uncached, we
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+ * assume SC).
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+ */
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+ switch (cca) {
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+ case CONF_CM_CACHABLE_CE:
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+ case CONF_CM_CACHABLE_COW:
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+ case CONF_CM_CACHABLE_CUW:
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+ mc = 1;
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+ break;
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+ default:
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+ mc = 0;
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+ break;
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+ }
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if ((c->processor_id & PRID_REV_MASK) >=
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PRID_REV_R4400) {
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- c->cputype = CPU_R4400SC;
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- __cpu_name[cpu] = "R4400SC";
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+ c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
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+ __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
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} else {
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- c->cputype = CPU_R4000SC;
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- __cpu_name[cpu] = "R4000SC";
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+ c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
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+ __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
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}
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}
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