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@@ -98,8 +98,11 @@ static u8 opcode_table[256] = {
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0, 0, 0, 0,
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/* 0x40 - 0x4F */
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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- /* 0x50 - 0x5F */
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- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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+ /* 0x50 - 0x57 */
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ /* 0x58 - 0x5F */
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+ ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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+ ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
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/* 0x60 - 0x6F */
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0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@@ -1153,6 +1156,16 @@ special_insn:
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case 0xf4: /* hlt */
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ctxt->vcpu->halt_request = 1;
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goto done;
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+ case 0x58 ... 0x5f: /* pop reg */
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+ dst.ptr = (unsigned long *)&_regs[b & 0x7];
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+
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+ if ((rc = ops->read_std(register_address(ctxt->ss_base,
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+ _regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt)) != 0)
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+ goto done;
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+
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+ register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
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+ dst.orig_val = dst.val; /* Disable writeback. */
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+ break;
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}
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goto writeback;
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